STM8S207K6 STMicroelectronics, STM8S207K6 Datasheet - Page 40
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STM8S207K6
Manufacturer Part Number
STM8S207K6
Description
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM
Manufacturer
STMicroelectronics
Datasheet
1.STM8S207M8.pdf
(103 pages)
Specifications of STM8S207K6
Max Fcpu
up to 24 MHz, 0 wait states @ fCPU≤ 16 MHz
Program
up to 128 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles
Data
up to 2 Kbytes true data EEPROM; endurance 300 kcycles
Ram
up to 6 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
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Memory and register map
Table 9.
40/103
0x00 5315 to
0x00 530A
0x00 530B
00 530C0x
0x00 530D
0x00 530E
0x00 532A
0x00 5300
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
0x00 5307
0x00 5308
0x00 5309
0x00 530F
0x00 5310
0x00 5311
0x00 5312
0x00 5313
0x00 5314
0x00 531F
0x00 5320
0x00 5321
0x00 5322
0x00 5323
0x00 5324
0x00 5325
0x00 5326
0x00 5327
0x00 5328
0x00 5329
Address
General hardware register map (continued)
Block
TIM2
TIM3
Register label
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCMR3
TIM3_CCMR1
TIM3_CCMR2
TIM2_CNTRH
TIM2_CCR1H
TIM2_CCR2H
TIM2_CCR3H
TIM3_CNTRH
TIM2_CCER1
TIM2_CCER2
TIM2_CNTRL
TIM3_CCER1
TIM3_CNTRL
TIM2_CCR1L
TIM2_CCR2L
TIM2_CCR3L
TIM2_ARRH
TIM2_PSCR
TIM3_PSCR
TIM2_ARRL
TIM2_EGR
TIM3_EGR
TIM2_CR1
TIM3_CR1
TIM2_SR1
TIM2_SR2
TIM3_SR1
TIM3_SR2
TIM2_IER
TIM3_IER
Doc ID 14733 Rev 12
Reserved area (11 bytes)
TIM2 capture/compare enable register 1
TIM2 capture/compare enable register 2
TIM3 capture/compare enable register 1
TIM3 capture/compare mode register 1
TIM3 capture/compare mode register 2
TIM2 capture/compare mode register 1
TIM2 capture/compare mode register 2
TIM2 capture/compare mode register 3
TIM2 capture/compare register 1 high
TIM2 capture/compare register 3 high
TIM2 capture/compare register 1 low
TIM2 capture/compare register 2 low
TIM2 capture/compare register 3 low
TIM2 capture/compare reg. 2 high
TIM3 event generation register
TIM2 auto-reload register high
TIM2 event generation register
TIM2 interrupt enable register
TIM3 interrupt enable register
TIM2 auto-reload register low
TIM2 prescaler register
TIM3 prescaler register
TIM2 control register 1
TIM3 control register 1
TIM3 status register 1
TIM3 status register 2
TIM2 status register 1
TIM2 status register 2
TIM2 counter high
TIM3 counter high
TIM2 counter low
TIM3 counter low
Register name
STM8S207xx, STM8S208xx
status
Reset
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00