ST72561R9-Auto STMicroelectronics, ST72561R9-Auto Datasheet - Page 178

• Manufacturer Part Number: ST72561R9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561R9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

LINSCI serial communication interface (LIN master/slave)
Note:
Note:
Note:
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It is recommended to combine the header detection function with Mute mode. Putting the
LINSCI in mute mode allows the detection of Headers only and prevents the reception of
any other characters.
This mode can be used to wait for the next header without being interrupted by the data
bytes of the current message in case this message is not relevant for the application.
Synch break detection (LHDM = 0)
When a LIN synch break is received:
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●
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●
In LIN slave mode, the FE bit detects all frame error which does not correspond to a break.
Identifier detection (LHDM = 1)
This case is the same as the previous one except that the LHDF and the RDRF flags are set
only after the entire header has been received (this is true whether automatic
resynchronization is enabled or not). This indicates that the LIN Identifier is available in the
SCIDR register.
During LIN synch field measurement, the SCI state machine is switched off: no characters
are transferred to the data register.
LIN slave parity
In LIN slave mode (LINE and LSLV bits are set) LIN parity checking can be enabled by
setting the PCE bit.
In this case, the parity bits of the LIN identifier field are checked. The identifier character is
recognized as the 3
The bits involved are the two MSB positions (7th and 8th bits if M = 0; 8th and 9th bits if
M = 0) of the identifier character. The check is performed as specified by the LIN
specification:
The RDRF bit in the SCISR register is set. It indicates that the content of the shift
register is transferred to the SCIDR register, a value of 0x00 is expected for a break.
The LHDF flag in the SCICR3 register indicates that a LIN synch break field has been
detected.
An interrupt is generated if the LHIE bit in the SCICR3 register is set and the I[1:0] bits
are cleared in the CCR register.
Then the LIN synch field is received and measured.
–
–
If automatic resynchronization is enabled (LASE bit = 1), the LIN synch field is not
transferred to the shift register: there is no need to clear the RDRF bit.
If automatic resynchronization is disabled (LASE bit = 0), the LIN synch field is
received as a normal character and transferred to the SCIDR register and RDRF is
set.
rd
received character after a break character (included):
Doc ID 12370 Rev 8
LIN Synch
Break
LIN Synch
Field
parity bits
Identifier
Field
ST72561-Auto