ST7MC1K4 STMicroelectronics, ST7MC1K4 Datasheet - Page 238

• Manufacturer Part Number: ST7MC1K4
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
• Manufacturer: STMicroelectronics

Specifications of ST7MC1K4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST7MC1xx/ST7MC2xx
10-BIT A/D CONVERTER (ADC) (Cont’d)
When a conversion is complete:
To read the 10 bits, perform the following steps:
1. Poll the EOC bit or wait for EOC interrupt
2. Read ADCDRLSB
3. Read ADCDRMSB
The EOC bit is reset by hardware once the AD-
CDRMSB is read.
To read only 8 bits, perform the following steps:
1. Poll the EOC bit or wait for EOC interrupt
2. Read ADCDRMSB
The EOC bit is reset by hardware once the AD-
CDRMSB is read.
Changing the conversion channel
The application can change channels during con-
version. In this case the current conversion is
stopped and the A/D converter starts converting
the newly selected channel.
ADCCR consistency
If an End Of Conversion event occurs after soft-
ware has read the ADCDRLSB but before it has
read the ADCDRMSB, there would be a risk that
the two values read would belong to different sam-
ples.
238/309
– The EOC bit is set by hardware
– An interrupt request is generated if the ADCIE
– The result is in the ADCDR registers and re-
bit in the MCCBCR register is set (see
6.4.7 on page
mains valid until the next conversion has end-
ed.
38).
section
To guarantee consistency:
Thus, it is mandatory to read the ADCDRMSB just
after reading the ADCDRLSB. Otherwise the AD-
CDR register will not be updated until the AD-
CDRMSB is read.
10.8.4 Low Power Modes
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed.
10.8.5 Interrupts
1)
section 6.4.7 on page
Mode
Wait
Halt
End of Conver-
sion
The ADCIE bit is in the MCCBCR register (see
– The ADCDRMSB and the ADCDRLSB are
– The ADCDRMSB and the ADCDRLSB are un-
Interrupt
locked when the ADCCRLSB is read
locked when the MSB is read or when ADON
is reset.
Event
Description
No effect on A/D Converter
A/D Converter disabled.
After wake up from Halt mode, the A/D
Converter requires a stabilization time
t
before accurate conversions can be
performed.
STAB
Event
EOC
Flag
(see Electrical Characteristics)
38)
ADCIE
Control
Enable
Bit
1)
from
Wait
Exit
Yes
from
Exit
Halt
No