ST92150JDV1QAuto STMicroelectronics, ST92150JDV1QAuto Datasheet - Page 414

• Manufacturer Part Number: ST92150JDV1QAuto
• Description: 8/16-bit single voltage Flash MCU family with RAM, E3 TM(emulated EEPROM), CAN 2.0B and J1850 BLPD
• Manufacturer: STMicroelectronics

Specifications of ST92150JDV1QAuto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
KNOWN LIMITATIONS (Cont’d)
13.4 SCI-A AND CAN INTERRUPTS
Description
SCI-A interrupt (I0 channel) and CAN interrupts
(channels E0, E1, F0, F1, G0, G1, H0, H1) do not
respond when the CPUCLK is prescaled (MODER
register).
Workaround
Avoid using CPU prescaler when SCI-A and/or
CAN interrupts are used in the application.
13.5 SCI-A MUTE MODE
13.5.1 Mute Mode Description
The SCI can be put in Mute mode waiting for an
Idle line detection or an Address Mark detection,
and discarding all other byte transmissions. This is
done by setting the RWU (Receiver wake-up) bit in
the SCICR2 register (R244, page 26). This bit can
be reset either by software, to leave the Mute
mode, or by hardware when a wake up condition
has been reached.
Figure 167. Mute Mode Mechanism on address mark
Consequence
The address byte is lost and the SCI-A is again in
Mute mode.
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1
Data Line
RDRF
RWU
Mute mode mechanism
data
int
Data Line
A received data is indicated by the RDRF (Read
Data Ready Flag) bit in the SCISR register (R240,
page 26). This status bit is evaluated at the end of
the stop bit. If the RWU bit is in the set state at the
end of the stop bit, the data is not loaded in the
data register and the RDRF bit is not set.
On the contrary, if the RWU bit is in the reset state
at the end of the stop bit the data is loaded in the
data register and the RDRF bit is set.
13.5.2 Limitation Description
The SCICR2 also contains the following configura-
tion bits: Interrupt Enable, Transmitter Enable, Re-
ceiver Enable and Send Break.
When the value of one of these bits is modified by
software, the SCICR2 register is read, its value is
modified and reloaded in the SCICR2 register. If
the SCI-A is in Mute mode during the read opera-
tion (RWU=1) and if an address mark event occurs
(resetting the RWU bit) before the write operation,
the RWU bit is set before the end of the stop bit. In
this case, the RDRF bit is not set, the data is not
received and no flag indicates the lost of the data.
13.5.3 Workaround
If you need to disable the SCI-A interrupt while it is
in Mute mode, use the global interrupt mask in the
dedicated interrupt controller, refer to Section 5.7
“Standard Interrupts” in the datasheet. Do not
change the TE, RE and SBK bits in the SCICR2
register while the SCI-A is in Mute mode.
RDRF
RWU
Corrupted Mute mode mechanism
ld r0,SCICR2
and r0,0x80
ld SCICR2, r0
under an SCICR2 access
data