ST72321J7 STMicroelectronics, ST72321J7 Datasheet - Page 42
ST72321J7
Manufacturer Part Number
ST72321J7
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST72321J7.pdf
(193 pages)
Specifications of ST72321J7
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt,Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST72321Rx ST72321ARx ST72321Jx
POWER SAVING MODES (Cont’d)
8.3 WAIT MODE
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to
42/193
Figure
25.
Figure 25. WAIT Mode Flow-chart
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
WFI INSTRUCTION
N
INTERRUPT
Y
OR SERVICE INTERRUPT
FETCH RESET VECTOR
256 OR 4096 CPU CLOCK
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
N
CYCLE DELAY
RESET
Y
XX
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
10
10
1)
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