ST72262G1 STMicroelectronics, ST72262G1 Datasheet - Page 158

• Manufacturer Part Number: ST72262G1
• Description: 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72262G1

• 4 K Or 8 Kbytes Program Memory: ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt,Wait and Slow
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes

ST72260Gx, ST72262Gx, ST72264Gx
ADC CHARACTERISTICS (Cont’d)
13.12.0.1 General PCB Design Guidelines
To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the noise-sensitive,
analog physical interface from noise generating
CMOS logic signals.
– Properly place components and route the signal
ADC Accuracy with f
Figure 100. ADC Accuracy Characteristics
Notes:
1. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the analog input pins significantly
reduces the accuracy of the conversion being performed on another analog input.
For I
for each 10KΩ increase of the external analog source impedance. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits spec-
ified for I
2. Refer to
158/172
Symbol
1023
1022
1021
traces on the PCB to shield the analog inputs.
|E
|E
|E
|E
|E
7
6
5
4
3
2
1
INJ-
0
O
G
D
T
L
V
|
|
|
|
|
=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 4 LSB
SS
INJ(PIN)
Digital Result ADCDR
“Typical values” on page 126
1LSB
1
Total unadjusted error
Offset error
Gain Error
Differential linearity error
Integral linearity error
E
O
and ΣI
2
IDEAL
3
Parameter
INJ(PIN)
1)
=
1)
CPU
V
------------------------------- -
4
DD
1024
=8 MHz, f
in
–
5
1 LSB
V
Section 13.8
SS
1)
1)
E
6
T
IDEAL
1)
E
7
L
for more information on typical ADC accuracy values.
ADC
(2)
=4 MHz R
does not affect the ADC accuracy.
Conditions
E
D
1021 1022 1023 1024
(3)
AIN
(1)
< 10
E
G
Analog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may
switch while the analog inputs are being sampled
by the A/D converter. Do not toggle digital out-
puts on the same I/O port as the A/D input being
converted.
Typ
kΩ,
V
1.5
4
1
1
3
DD
2)
V
FLASH
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
E
between the actual and the ideal transfer curves.
E
transition and the first ideal one.
E
transition and the last actual one.
E
between actual steps and the ideal one.
E
between any actual transition and the end point
correlation line.
DD
T
O
G
D
L
=Total Unadjusted Error: maximum deviation
=Integral Linearity Error: maximum deviation
=Offset Error: deviation between the first actual
=Gain Error: deviation between the last ideal
=Differential Linearity Error: maximum deviation
= 4.5V to 5.5V
V
Max
in
4.5
4.5
4.5
6
5
(LSB
IDEAL
Typ
)
TBD
TBD
TBD
TBD
TBD
2)
ROM
Max
TBD
TBD
TBD
TBD
TBD
Unit
LSB