STR910FAW32 STMicroelectronics, STR910FAW32 Datasheet - Page 79

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STR910FAW32

Manufacturer Part Number
STR910FAW32
Description
32-bit MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of STR910FAW32

Arm966e-s Risc Core
Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

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STR91xFAxxx
Table 36.
Symbol
t
t
t
t
t
t
RCR
RDH
t
RAS
RDS
t
AAS
AAH
AW
RP
Read to CSn
inactive
Read address setup
time
Read data setup
time
Read data hold time
Read pulse width
ALE pulse width
Address to ALE
setup time
Address to ALE
hold time
Mux read
Figure 21. Mux read diagram
Mux read times
Parameter
EMI_A D[15:0]
EMI_CSxn
EMI_A [23:16]
EMI_A LE
EMI_RDn
((WSTRD-WSTOEN+1) x t
(ALE_LENGTH x t
(ALE_LENGTH x t
((WSTOEN) x t
(t
BCLK
Doc ID 13495 Rev 6
t
t
AW
AAS
12 ns
Min
/2)- 1 ns
A ddress
0
0
BCLK
t
BCLK
BCLK
RA S
BCLK
)- 4 ns
) - 3.5 ns
) - 3.5 ns
A ddress
t
) - 0.5 ns ((WSTRD-WSTOEN+1) x t
AAH
Value
(ALE_LENGTH x t
(ALE_LENGTH x t
t
RP
((WSTOEN) x t
Electrical characteristics
(t
t
Data
RDS
BCLK
t
1.5 ns
RCR
Max
/2) + 2 ns
-
BCLK
BCLK
BCLK
BCLK
t
RDH
)
) + 2.5 ns
)
)
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