STR750FV0 STMicroelectronics, STR750FV0 Datasheet - Page 65

• Manufacturer Part Number: STR750FV0
• Description: 32-bit MCU
• Manufacturer: STMicroelectronics

Specifications of STR750FV0

• Smart Low Power Modes: SLOW, WFI, STOP and STANDBY with backup registers
• Conversion Time: min. 3.75 μs

STR750Fxx STR751Fxx STR752Fxx STR755Fxx
SSP synchronous serial peripheral in slave mode (SPI or TI mode)
Subject to general operating conditions with C
Table 39.
1. Data based on characterisation results, not tested in production.
Figure 33. SPI configuration, slave mode with CPHA=0, single transfer
MISO
MOSI
t
Symbol
t
t
t
t
t
t
su(MOSI)
NSSLQV
t
NSSLQZ
su(NSS)
h(MOSI)
SCKQV
SCKQX
h(NSS)
f
SCK
NSS
CPHA=0
CPOL=0
CPHA=0
CPOL=1
OUTPUT
INPUT
INPUT
DONT CARE
SPI clock frequency
NSS input setup time w.r.t
SCK first edge
NSS input hold time w.r.t
SCK last edge
NSS low to Data Output
MISO valid time
NSS low to Data Output
MISO invalid time
SCK trigger edge to data
output MISO valid time
SCK trigger edge to data
output MISO invalid time
MOSI setup time w.r.t SCK
sampling edge
MOSI hold time w.r.t SCK
sampling edge
SSP slave mode characteristics
t
z
NSSLQV
t
su(NSS)
Parameter
t
su(SI)
sample
edge
MSB IN
t
h(SI)
t
t
w(SCKH)
w(SCKL)
MSB OUT
trigger
t
SCKQV(MISO)
edge
t
c(SCK)
Conditions
BIT OUT
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
L
(1)
≈
45 pF
BIT1 IN
3t
3t
t
t
PCLK
PCLK
PCLK
PCLK
t
SCKQX(MISO)
2t
2t
2t
2t
2t
2t
Min
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
0
0
0
0
+15ns
+15ns
+15 ns
+15 ns
sample
edge
t
t
r(SCK)
f(SCK)
Electrical parameters
LSB IN
3t
3t
3t
3t
(f
LSB OUT
2.66 MHz
PCLK
PCLK
PCLK
PCLK
trigger
PLCK
edge
Max
t
15
30
h(NSS)
+30 ns
+30 ns
+15 ns
+15 ns
/12)
t
NSSHQZ
DONT CARE
MHz
Unit
ns
65/84
z