ST7MC2R6 STMicroelectronics, ST7MC2R6 Datasheet - Page 214
ST7MC2R6
Manufacturer Part Number
ST7MC2R6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2R6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Bits 2:0 = VR[2:0]: BEMF/demagnetisation Refer-
These bits select the Vref value as shown in the
Table
Demagnetisation detection.
Table 64. Threshold voltage setting
*Typical values for V
214/309
VR2
ence threshold
1
1
1
1
0
0
0
0
64. The Vref value is used for BEMF and
VR1
1
1
0
0
1
1
0
0
VR0
1
0
1
0
1
0
1
0
DD
Threshold voltage set by ex-
Vref voltage threshold
=5V
ternal MCVREF pin
3.5V*
2.5V*
1.5V*
0.6V*
0.2V*
2V*
1V*
PHASE STATE REGISTER (MPHST)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = IS[1:0]*: Input Selection bits
These bits mainly select the input to connect to
comparator as shown in
figuration (IS[1:0] = 11) specifies that an incremen-
tal encoder is used (in that case MCIA and MCIB
digital signals are directly connected to the incre-
mental encoder interface and the analog multi-
plexer is bypassed.
Table 65. Input Channel Selection
Bits 5:0 =OO[5:0]*: Channel On/Off bits
These bits are used to switch channels on/off at
the next C event if the DAC bit =0 or directly if
DAC=1
0: Channel Off, the relevant switch is OFF, no
1: Channel On the relevant switch is ON, PWM is
Table 66. OO[5:0] Bit Meaning
* Preload bits, new value taken into account at
next C event.
Caution: As the MPHST register contains bits with
preload, the whole register has to be written at
once. This means that a Bit Set or Bit Reset in-
struction on only one bit without preload will have
the effect of resetting all the bits with preload.
IS1*
IS1
PWM possible
possible (not signifiant when PCN or DTE bit is
set).
7
0
0
1
1
IS0*
6
IS0
OO[5:0]
0
1
0
1
0
1
OO5*
5
Both MCIA and MCIB: Encoder Mode
OO4*
4
Channel selected
Table
OO3*
3
Output Channel State
MCIA
MCIB
MCIC
65. The fourth con-
OO2*
2
Inactive
Active
OO1*
1
OO0*
0
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