ST72321R6-Auto STMicroelectronics, ST72321R6-Auto Datasheet - Page 125

• Manufacturer Part Number: ST72321R6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321R6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
14.3.4
Note:
14.3.5
Note:
14.3.6
Note:
Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1.
The slave must have the same CPOL and CPHA settings as the master.
2.
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
–
–
An access to the SPICSR register while the SPIF bit is set
A read to the SPIDR register.
Write to the SPICSR register to perform the following actions:
a)
b)
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
–
–
An access to the SPICSR register while the SPIF bit is set
A write or a read to the SPIDR register
The SPIF bit is set by hardware
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see
Manage the SS pin as described in
Figure
be held low during byte transmission and pulled up between each byte to let the
slave write in the shift register.
The SPIF bit is set by hardware.
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Figure
57. If CPHA = 1, SS must be held low continuously. If CPHA = 0, SS must
59).
Doc ID 13829 Rev 1
Slave select management on page 123
Serial peripheral interface (SPI)
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