ST10F269Z2 STMicroelectronics, ST10F269Z2 Datasheet - Page 39

• Manufacturer Part Number: ST10F269Z2
• Description: 16-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST10F269Z2

• Single Voltage Supply: 5V ±10% (EMBEDDED REGULATOR FOR 2.7 or 3.3 V CORE SUPPLY).
• Temperature Ranges: -40 +125 °C / -40 to 85 °C

ST10F269
Table 4 : Instruction Set Summary
6.3 - MAC Coprocessor Specific Instructions
The following table gives an overview of the MAC
instruction set. All the mnemonics are listed with
the addressing modes that can be used with each
instruction.
For each combination of mnemonic and address-
ing mode this table indicates if it is repeatable or
not.
New addressing capabilities enable the CPU to
supply the MAC with up to 2 operands per instruc-
tion cycle. MAC instructions: multiply, multi-
ply-accumulate,
operations and the CoMOV transfer instruction
have been added to the standard instruction set.
Full details are provided in the ‘ST10 Family Pro-
gramming Manual’. Double indirect addressing
requires two pointers. Any GPR can be used for
one pointer, the other pointer is provided by one of
JNBS
CALLA, CALLI, CALLR
CALLS
PCALL
TRAP
PUSH, POP
SCXT
RET
RETS
RETP
RETI
SRST
IDLE
PWRDN
SRVWDT
DISWDT
EINIT
ATOMIC
EXTR
EXTP(R)
EXTS(R)
NOP
Mnemonic
32-bit
Jump relative and set bit if direct bit is not set
Call absolute/indirect/relative subroutine if condition is met
Call absolute subroutine in any code segment
Push direct word register onto system stack and call absolute subroutine
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
Push direct word register onto system stack and update register with word
operand
Return from intra-segment subroutine
Return from inter-segment subroutine
Return from intra-segment subroutine and pop direct
word register from system stack
Return from interrupt service subroutine
Software Reset
Enter Idle Mode
Enter Power Down Mode (supposes NMI-pin being low)
Service Watchdog Timer
Disable Watchdog Timer
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Null operation
signed
arithmetic
Description
two specific SFRs IDX0 and IDX1. Two pairs of
offset registers QR0/QR1 and QX0/QX1 are asso-
ciated with each pointer (GPR or IDX
The GPR pointer allows access to the entire
memory space, but IDX
Dual-Port RAM, except for the CoMOV instruction.
6 - CENTRAL PROCESSING UNIT (CPU)
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