ST72361K6 STMicroelectronics, ST72361K6 Datasheet - Page 37

• Manufacturer Part Number: ST72361K6
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72361K6

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

8 POWER SAVING MODES
8.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, five main pow-
er saving modes are implemented in the ST7 (see
Figure
■
■
■
■
■
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
(f
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 22. Power Saving Mode Transitions
OSC2
Slow
Wait (and Slow-Wait)
Active Halt
Auto Wake-up From Halt (AWUFH)
Halt
AUTO WAKE-UP FROM HALT
).
22):
ACTIVE HALT
SLOW WAIT
POWER CONSUMPTION
SLOW
WAIT
HALT
RUN
Low
High
8.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
– To adapt the internal clock frequency (f
SLOW mode is controlled by three bits in the
MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f
In this mode, the master clock frequency (f
can be divided by 2, 4, 8 or 16. The CPU and pe-
ripherals are clocked at this lower frequency
(f
Note: SLOW-WAIT mode is activated by entering
WAIT mode while the device is in SLOW mode.
Figure 23. SLOW Mode Clock Transitions
CPU
internal clock in the device,
the available supply voltage.
).
CP1:0
f
SMS
CPU
f
OSC2
f
FREQUENCY
OSC2
00
NEW SLOW
REQUEST
/2
01
CPU
f
OSC2
NORMAL RUN MODE
).
/4
REQUEST
ST72361
CPU
f
OSC2
37/225
OSC2
) to
)