STR730FZ2 STMicroelectronics, STR730FZ2 Datasheet - Page 20

• Manufacturer Part Number: STR730FZ2
• Description: 32-BIT ARM7 FLASH MICROCONTROLLER WITH 3x CAN, 4 UARTs, 20 TIMERS, ADC, 12 COMM. INTERFACES
• Manufacturer: STMicroelectronics

Specifications of STR730FZ2

• 5 Power Saving Modes: SLOW, WFI, LPWFI, STOP and HALT modes
• 6/10 16-bit Timers (tim) Each With: 2 input captures, 2 output compares, PWM and pulse counter modes
• Conversion Time: min. 3μs, range

Block diagram
3.3
20/52
Memory mapping
Figure 5
memory map (from 0x0000_0000 to 0xFFFF_FFFF) is shown on the left part of the figure,
the right part shows maps of the Flash and APB areas. For flexibility the Flash or RAM
addresses can be aliased to Block 0 addresses using the remapping feature
Most reserved memory spaces (gray shaded areas in
by the user code. When an access this memory space is attempted, an ABORT signal is
generated. Depending on the type of access, the ARM processor will enter “prefetch abort”
state (Exception vector 0x0000_000C) or “data abort” state (Exception vector
0x0000_0010). It is up to the application software to manage these abort exceptions.
Figure 5.
0xFFFF FFFF
0xFFFF 8000
0xE000 0000
0xDFFF FFFF
0xC000 0000
0xBFFF FFFF
0xA000 3FFF
0xA000 0000
0x9FFF FFFF
0x8010 0017
0x8000 0000
0x7FFF FFFF
0x6000 03FF
0x6000 0000
0x5FFF FFFF
0x4000 003F
0x4000 0000
0x3FFF FFFF
0x2000 0000
0x1FFF FFFF
0x0010 0017
0x0000 0000
0x2000 000F
Addressable memory space
7
6
5
4
3
2
1
0
shows the various memory configurations of the STR73xF system. The system
NATIVE ARBITER
CONFIG. REGS
APB TO ARM7
4 Gbytes
Memory map
BRIDGE
Flash
PRCCU
Flash
(4) Only available in STR730/STR731
RAM
(3) Only available in STR73xZ2/V2 and STR73xZ1/V1
(1) Flash aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes)
(2) Only available in STR73xZ2/V2
(1)
64B
16B
16K
64K/128K/256K
32K
1K
64K/128K/256K
0x8010 DFFF
0x8010 C000
0x8010 0017
0x8010 0000
0x8003 FFFF
0x8003 0000
0x8002 FFFF
0x8002 0000
0x8001 FFFF
0x8001 0000
0x8000 FFFF
0x8000 8000
0x8000 7FFF
0x8000 6000
0x8000 5FFF
0x8000 4000
0x8000 3FFF
0x8000 2000
0x8000 1FFF
0x8000 0000
64K/128/256 Kbytes
Flash memory space
System Memory
Flash registers
B0F7
B0F6
B0F5
B0F4
B0F3
B0F2
B0F1
B0TF
(2)
(2)
(3)
8K
20B
64K
64K
64K
32K
8K
8K
8K
8K
Figure
access to gray shaded area will return an ABORT
5) are protected from access
0xFFFF FFFF
0xFFFF FC00
0xFFFF FBFF
0xFFFF F800
0xFFFF F7FF
0xFFFF F600
0xFFFF F400
0xFFFF F3FF
0xFFFF F000
0xFFFF EFFF
0xFFFF EC00
0xFFFF EBFF
0xFFFF E800
0xFFFF E7FF
0xFFFF E400
0xFFFF E3FF
0xFFFF E000
0xFFFF DFFF
0xFFFF DC00
0xFFFF DBFF
0xFFFF D800
0xFFFF D7FF
0xFFFF D400
0xFFFF D3FF
0xFFFF D000
0xFFFF CFFF
0xFFFF CC00
0xFFFF CBFF
0xFFFF C800
0xFFFF C7FF
0xFFFF C400
0xFFFF C3FF
0xFFFF C000
0xFFFF BFFF
0xFFFF BC00
0xFFFF BBFF
0xFFFF B800
0xFFFF B7FF
0xFFFF B400
0xFFFF B3FF
0xFFFF B000
0xFFFF AFFF
0xFFFF AC00
0xFFFF ABFF
0xFFFF A800
0xFFFF A7FF
0xFFFF A600
0xFFFF A400
0xFFFF A3FF
0xFFFF A200
0xFFFF A000
0xFFFF 9FFF
0xFFFF 9E00
0xFFFF 9C00
0xFFFF 9BFF
0xFFFF 9800
0xFFFF 97FF
0xFFFF 9400
0xFFFF 93FF
0xFFFF 9000
0xFFFF 8FFF
0xFFFF 8C00
0xFFFF 8BFF
0xFFFF 8800
0xFFFF 87FF
0xFFFF 8400
0xFFFF 83FF
0xFFFF 8000
APB memory space
APB BRIDGE 1 REGS
APB BRIDGE 0 REGS
32 Kbytes
WAKEUPTIM
GP I/O 0-6
WAKEUP
DMA 0-3
PWM 0-5
reserved
reserved
reserved
reserved
reserved
CAN 2
CAN 1
CAN 0
UART 3
UART 1
UART 2
UART 0
TIM 5-9
BSPI 2
BSPI 1
BSPI 0
TB 0-2
TIM 4
TIM 3
TIM 2
TIM 1
TIM 0
WDG
CMU
I
I
ADC
RTC
EIC
2
2
Drawing not to scale
C 1
C 0
(4)
(4)
(4)
STR73xFxx
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K