ST7LIT19BY0 STMicroelectronics, ST7LIT19BY0 Datasheet - Page 24
ST7LIT19BY0
Manufacturer Part Number
ST7LIT19BY0
Description
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
Manufacturer
STMicroelectronics
Datasheet
1.ST7LIT10BF0.pdf
(159 pages)
Specifications of ST7LIT19BY0
Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention
20 years at 55˚C.
128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55˚C.
Clock Sources
Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow
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ST7LITE1xB
– The x8 PLL is intended for operation with V
Refer to
tion.
If the PLL is disabled and the RC oscillator is ena-
bled, then f
If both the RC oscillator and the PLL are disabled,
f
Figure 13. PLL Output Frequency Timing
Diagram
When the PLL is started, after reset or wake up
from Halt mode or AWUFH mode, it outputs the
clock after a delay of t
24/159
1
OSC
the 3.3V to 5.5V range
4/8 x
input
freq.
is driven by the external clock.
t
STARTUP
Section 15.1
OSC =
t
LOCK
1MHz.
STARTUP
for the option byte descrip-
1)
LOCKED bit set
t
.
STAB
DD
t
in
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACC
a stabilization time of t
13.3.5 Internal RC Oscillator and
Refer to
of the LOCKED bit in the SICSR register.
Note 1:
It is possible to obtain f
5.5V range with internal RC and PLL enabled by
selecting 1MHz RC and x8 PLL and setting the
PLLdiv2 bit in the PLLTST register (see
7.6.4 on page
section 7.6.4 on page 35
35).
OSC
STAB
= 4MHz in the 3.3V to
(see
PLL
) is reached after
PLL)
for a description
Figure 13
section
and
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