ST72264G2 STMicroelectronics, ST72264G2 Datasheet - Page 113
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ST72264G2
Manufacturer Part Number
ST72264G2
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet
1.ST72262G2.pdf
(172 pages)
Specifications of ST72264G2
4 K Or 8 Kbytes Program Memory
ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
4 Power Saving Modes
Halt, Active Halt,Wait and Slow
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes
- Current page: 113 of 172
- Download datasheet (2Mb)
I
I
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = FM/SM Fast/Standard I
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
0: Standard I
1: Fast I
Bit 6:0 = CC[6:0] 7-bit clock divider.
These bits select the speed of the bus (F
pending on the I
when the interface is disabled (PE=0).
Refer to the Electrical Characteristics section for
the table of values.
Note: The programmed F
SCL and SDA lines.
FM/SM
2
2
C BUS INTERFACE (Cont’d)
C CLOCK CONTROL REGISTER (CCR)
7
CC6
2
C mode
2
CC5
C mode
2
C mode. They are not cleared
CC4
SCL
CC3
assumes no load on
2
C mode.
CC2
CC1
SCL
CC0
) de-
0
I
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[7:0] 8-bit Data Register.
These bits contain the byte to be received or trans-
mitted on the bus.
– Transmitter mode: Byte transmission start auto-
– Receiver mode: the first data byte is received au-
2
C DATA REGISTER (DR)
matically when the software writes in the DR reg-
ister.
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the following data bytes are received one
by one after reading the DR register.
D7
7
ST72260Gx, ST72262Gx, ST72264Gx
D6
D5
D4
D3
D2
D1
113/172
D0
0
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