STR912FAZ46 STMicroelectronics, STR912FAZ46 Datasheet - Page 22

• Manufacturer Part Number: STR912FAZ46
• Description: ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
• Manufacturer: STMicroelectronics

Specifications of STR912FAZ46

• Arm966e-s Risc Core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

Functional overview
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Flash memory interface clock (FMICLK)
The FMICLK clock is an internal clock derived from RCLK, defaulting to RCLK frequency at
power up. The clock can be optionally divided by 2. The FMICLK determines the bus
bandwidth between the ARM core and the Flash memory. Typically, codes in the Flash
memory can be fetched one word per FMICLK clock in burst mode. The maximum FMICLK
frequency is 96 MHz.
UART and SSP clock (BRCLK)
BRCLK is an internal clock derived from f
and to generate the Baud rate for the three on-chip UART peripherals. The frequency can
be optionally divided by 2.
External memory interface bus clock (BCLK)
The BCLK is an internal clock that controls the EMI bus. All EMI bus signals are
synchronized to the BCLK. The BCLK is derived from the HCLK and the frequency can be
configured to be the same or half that of the HCLK. Refer to
maximum BCLK frequency (f
an output pin.
USB interface clock
Special consideration regarding the USB interface: The clock to the USB interface must
operate at 48 MHz and comes from one of three sources, selected under firmware control:
●
●
●
Ethernet MAC clock
Special consideration regarding the Ethernet MAC: The external Ethernet PHY interface
device requires it’s own 25 MHz clock source. This clock can come from one of two sources:
●
●
External RTC calibration clock
The RTC_CLK can be enabled as an output on the JRTCK pin. The RTC_CLK is used for
RTC oscillator calibration. The RTC_CLK is active in Sleep mode and can be used as a
system wake up control clock.
CCU master clock output of 48 MHz.
CCU master clock output of 96 MHz. An optional divided-by-two circuit is available to
produce 48 MHz for the USB while the CPU system runs at 96MHz.
STR91xFA pin P2.7. An external 48 MHz oscillator connected to pin P2.7 can directly
source the USB while the CCU master clock can run at some frequency other than 48
or 96 MHz.
A 25 MHz clock signal coming from a dedicated output pin (P5.2) of the STR91xFA. In
this case, the STR91xFA must use a 25 MHz signal on its main oscillator input in order
to pass this 25 MHz clock back out to the PHY device through pin P5.2. The advantage
here is that an inexpensive 25 MHz crystal may be used to source a clock to both the
STR91xFA and the external PHY device.
An external 25 MHz oscillator connected directly to the external PHY interface device.
In this case, the STR91xFA can operate independent of 25 MHz.
BCLK
Doc ID 13495 Rev 6
). The BCLK clock is available on the LFBGA package as
MSTR
that is used to drive the two SSP peripherals
Table 17 on page 66
STR91xFAxxx
for the