STM1811 STMicroelectronics, STM1811 Datasheet - Page 9

• Manufacturer Part Number: STM1811
• Description: Low Power Reset Circuit
• Manufacturer: STMicroelectronics

Specifications of STM1811

• Operating Temperature: –40 °C to 105 °C
• ± 2.5% Reset Threshold Accuracy: (–40 °C to 105 °C)

STM1810/1811/1812/1813/1815/1816/1817/1818
2
2.1
2.2
2.3
2.4
Operation
Reset output
The STM181x asserts a reset signal to the microcontroller (MCU) whenever V
below the reset threshold (V
105 °C). A microcontroller’s (MCU) reset input starts the MCU in a known state. The
STM1810 - STM1813/ STM1815 - STM1818 low power reset circuits assert reset to prevent
code-execution errors during power-up, power-down, and brownout conditions
During power-up, once V
the reset time-out period, t
If V
low for at least the reset time-out period. Any time V
internal timer clears. The reset timer starts when V
Reset t
(STM1813/STM1818), following a low signal of 1.5 µs minimum duration.
Push-button detect reset (STM1813/1818)
Many systems require push-button reset capability
logic circuitry to initiate reset. On the STM1813/STM1818, a logic low on RST held for
greater than 1.5 µs asserts a reset. RST deasserts following a 100 ms minimum reset time-
out delay (t
100 ms minimum reset time-out delay. To facilitate use with mechanical switches, the
STM1813/STM1818 contain internal debounce circuitry. A debounced waveform is shown in
Figure 9
Interfacing to bidirectional microcontrollers (MCU’s)
As the RST output on the STM1811/STM1816 is open-drain, these devices interface easily
with MCU’s that have bidirectional reset pins. Connecting the µP supervisor’s reset (RST)
output directly to the microcontroller’s reset (RST) pin allows either device to assert reset
(Figure
Negative going V
The STM181x are relatively immune to negative-going V
shows typical transient duration versus reset comparator overdrive (for which the STM181x
will NOT generate a reset pulse). The graph was generated using a negative pulse applied
to V
magnitude indicated (comparator overdrive). The graph indicates the maximum pulse width
a negative V
transient increases (further below the threshold), the maximum allowable pulse width
decreases. Any combination of duration and overdrive which lies under the curve will NOT
generate a reset signal. Typically, a V
threshold and lasts 20 µs or less will not cause a reset pulse. A 0.1 µF bypass capacitor
mounted as close as possible to the V
CC
CC,
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
rec
starting at 0.5 V above the actual reset threshold and ending below it by the
10). No external pull-up resistor is required, as it is within the STM1811/STM1816.
The RST output has an internal 5.5 kΩ pull-up resistor.
is also triggered by an externally initiated rising edge on the RST pin
rec
CC
). A manual reset input shorter than 1.5 µs may release RST without the
transient can have without causing a reset pulse. As the magnitude of the
CC
CC
rec
exceeds the reset threshold an internal timer keeps RST low for
RST
. After this interval, RST returns high.
transients
Doc ID11464 Rev 8
), and is guaranteed valid down to V
CC
CC
transient that goes 100 mV below the reset
pin provides additional transient immunity.
CC
(Figure
CC
returns above the reset threshold.
goes below the reset threshold, the
CC
8), allowing the user or external
transients (glitches).
CC
= 1.0 V (0 °C to
CC
(Figure
Figure 19
Operation
goes
7).
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