STM6519 STMicroelectronics, STM6519 Datasheet - Page 5

• Manufacturer Part Number: STM6519
• Description: 4-pin Smart Reset™
• Manufacturer: STMicroelectronics

Specifications of STM6519

• Option 1: fully push-button controlled, no fixed or minimum pulse width guaranteed
• Option 2: defined output reset pulse duration (tREC), factory-programmed
• Operating Temperature: -40 °C to +85 °C

STM6519
1
1.1
Description
The Smart Reset
reset push-button closures do not cause system resets. This is done by implementing an
extended Smart Reset input delay time (t
the need for a specific dedicated reset button.
This reset configuration provides versatility and allows the application to distinguish between
a software generated interrupt and a hard system reset. When the input push-button is
connected to the microcontroller interrupt input, and is closed for a short time, the processor
can only be interrupted. If the system still does not respond properly, continuing to keep the
push-buttons closed for the extended setup time t
through the reset output.
The STM6519 has one Smart Reset input (SR) with preset delayed Smart Reset setup time
(t
selected t
inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset
pulse duration is fixed for t
a broad V
Test mode
After pulling SR up to V
shortened t
t
option is not used). This is feedback, and the user only knows that the device is locked in
test mode. Each time the SR input is connected to ground in test mode, a shortened
t
can be quickly tested without repeating test mode triggering. Return to normal mode is
possible by performing a new startup of the device (i.e. V
original state).
The advantages of this solution are its high glitch immunity, user feedback regarding entry
into test mode, and testability within the full V
REC
SRC-SHORT
SRC
(if t
). The reset output (RST) is asserted after the Smart Reset input is held active for the
REC
SRC
CC
SRC-INI
(t
option is used) or stays low as long as overvoltage on SR is detected (if t
range from 2.0 V to 5.5 V.
SRC
delay time. The RST output remains asserted either until the SR input goes to
TM
/128) is used instead of regular t
(42 ms, typ.). After t
devices provide a useful feature which ensures that inadvertent short
TEST
REC
(V
Doc ID 022111 Rev 4
(i.e. factory-programmed). The device fully operates over
CC
+ 1.4 V) or above, the counter starts to count the initial
SRC-INI
SRC
), which ensures a safe reset and eliminates
CC
expires, the RST output either goes down for
range.
SRC
SRC
causes a hard reset of the processor
(0.5 s - 10 s). In this way the device
CC
goes to 0 V and back to its
Description
REC
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