STM818L/M STMicroelectronics, STM818L/M Datasheet - Page 13

• Manufacturer Part Number: STM818L/M
• Description: 5V Supervisor
• Manufacturer: STMicroelectronics

Specifications of STM818L/M

• Operating Temperature: –40 °C to +85 °C (industrial grade)

STM690A/692A/703/704/802/805/817/818/819
2
2.1
2.2
2.3
Note:
1
2
Operation
Reset output
The STM690A/692A/703/704/802/805/817/818/819 Supervisor asserts a reset signal to the
MCU whenever V
when the Push-button Reset Input (MR) is taken low. RST is guaranteed to be a logic low
(logic high for STM805) for 0V < V
battery, RST is guaranteed valid down to V
During power-up, once V
the reset time-out period, t
If V
low for at least the reset time-out period (t
the internal timer clears. The reset timer starts when V
Push-button reset input (STM703/704/819)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t
Figure
it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain/collector outputs. Connect a normally open momentary switch from MR to GND
to create a manual reset function; external debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor
from MR to GND to provide additional noise immunity. MR may float, or be tied to V
not used.
Watchdog input (NOT available on STM703/704/819)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the Watchdog Input (WDI) within t
watchdog timer is cleared by either:
1.
2.
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting (see
The watchdog function may be disabled by floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and
the maximum allowable load capacitance is 200 pF.
Input pulses less than 20 ns will be ignored.
CC
a reset pulse, or
by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns.
If WDI is tied high or low, a reset pulse is triggered every 1.8 sec (t
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
41) after it returns high. The MR input has an internal 40 k pull-up resistor, allowing
CC
goes below the reset threshold (V
CC
rec
exceeds the reset threshold an internal timer keeps RST low for
. After this interval RST returns high.
Doc ID 10522 Rev 10
CC
< V
WD
RST
rec
CC
(1.6 sec typ), the reset is asserted. The internal
). Any time V
if V
=1 V.
Figure
BAT
is greater than 1 V. Without a backup
RST)
CC
42).
CC
returns above the reset threshold.
, a watchdog time-out occurs, or
goes below the reset threshold
WD
+ t
rec
).
Operation
CC
rec
when
(see
13/43