DS2413 Maxim, DS2413 Datasheet - Page 6

• Manufacturer Part Number: DS2413
• Description: The DS2413 is a dual-channel programmable I/O 1-Wire® chip
• Manufacturer: Maxim

PIO STUCTURE
Each PIO consists of an open-drain pulldown transistor with 28V capability. The transistor is controlled by the PIO
Output Latch, as shown in Figure 5. The PIO Control unit connects the PIOs to the 1-Wire interface.
Figure 5. PIO Simplified Logic Diagram
PIO FUNCTION COMMANDS
The PIO Function Flow Chart (Figure 6) describes the protocols necessary to access the PIO pins of the DS2413.
Examples on how to use these functions are included at the end of this document. The communication between
master and DS2413 takes place either at standard speed (default, OD = 0) or at Overdrive Speed (OD = 1). If not
explicitly set into the Overdrive Mode, the DS2413 powers up in standard speed.
PIO ACCESS READ [F5h]
This command reads the PIO logical status and reports it together with the state of the PIO Output Latch in an
endless loop. A PIO Access Read can be terminated at any time with a 1-Wire Reset.
PIO Status Bit Assignment
The state of both PIO channels is sampled at the same time. The first sampling occurs during the last (most
significant) bit of the command code F5h. The PIO status is then reported to the bus master. While the master
receives the last (most significant) bit of the PIO status byte, the next sampling occurs and so on until the master
generates a 1-Wire Reset. The sampling occurs with a delay of t
previous byte, as shown in Figure 7. The value of "x" is approximately 0.2µs.
Figure 7. PIO Access Read Timing Diagram
Notes:
1
2
b7
Complement of b3 to b0
The "previous byte" could be the command code or the data byte resulting from the previous PIO sample.
The sample point timing also applies to the PIO Access Write command, with the "previous byte" being the
write confirmation byte (AAh).
b6
Latch State.
PIO Output
PIO Clock
PIO Data
b5
PIO Pin
State
b4
IO
PIOB Output
Latch State
b3
MS 2 bits of
previous byte
t
CLOCK
REH
+x
V
Sampling Point
TH
PIOB Pin
State
b2
6 of 18
PIO Out-
put Latch
D
Q
Q
PIOA Output
LS 2 bits of PIO
Status byte
Latch State
REH
b1
+x from the rising edge of the MS bit of the
PIOA Pin
State
b0
PIO Pin