DS2431 Maxim, DS2431 Datasheet

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DS2431

Manufacturer Part Number
DS2431
Description
The DS2431 is a 1024-bit, 1-Wire® EEPROM chip organized as four memory pages of 256 bits each
Manufacturer
Maxim
Datasheet

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The DS2431 is a 1024-bit, 1-Wire
nized as four memory pages of 256 bits each. Data is
written to an 8-byte scratchpad, verified, and then
copied to the EEPROM memory. As a special feature, the
four memory pages can individually be write protected or
put in EPROM-emulation mode, where bits can only be
changed from a 1 to a 0 state. The DS2431 communi-
cates over the single-conductor 1-Wire bus. The commu-
nication follows the standard 1-Wire protocol. Each
device has its own unalterable and unique 64-bit ROM
registration number that is factory lasered into the chip.
The registration number is used to address the device in
a multidrop, 1-Wire net environment.
19-4675; Rev 12; 2/12
Pin Configurations appear at end of data sheet.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Accessory/PCB Identification
Medical Sensor Calibration Data Storage
Analog Sensor Calibration Including IEEE
P1451.4 Smart Sensors
Ink and Toner Print Cartridge Identification
After-Market Management of Consumables
V
CC
μC
Typical Operating Circuit
________________________________________________________________ Maxim Integrated Products
General Description
R
PUP
®
EEPROM chip orga-
Applications
IO
DS2431
GND
1024-Bit, 1-Wire EEPROM
♦ 1024 Bits of EEPROM Memory Partitioned Into
♦ Individual Memory Pages Can Be Permanently
♦ Switchpoint Hysteresis and Filtering to Optimize
♦ IEC 1000-4-2 Level 4 ESD Protection (±8kV
♦ Reads and Writes Over a Wide Voltage Range
♦ Communicates to Host with a Single Digital
♦ Also Available as Automotive Version Meeting
Note: The leads of TO-92 packages on tape and reel are
formed to approximately 100-mil (2.54mm) spacing. For
details, refer to the package outline drawing.
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
* EP = Exposed pad.
DS2431+
DS2431+T&R
DS2431P+
DS2431P+T&R
DS2431G+U
DS2431G+T&R
DS2431GA+U
DS2431GA+T&R
DS2431Q+T&R
DS2431X-S+
DS2431X+
Four Pages of 256 Bits
Write Protected or Put in EPROM-Emulation Mode
(“Write to 0”)
Performance in the Presence of Noise
Contact, ±15kV Air, Typical)
from 2.8V to 5.25V from -40°C to +85°C
Signal at 15.4kbps or 125kbps Using 1-Wire
Protocol
AEC-Q100 Grade 1 Qualification Requirements
(DS2431-A1; Refer to the IC Data Sheet for
Details)
PART
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
TEMP RANGE
Ordering Information
PIN-PACKAGE
3 TO-92
3 TO-92
6 TSOC
6 TSOC
2 SFN (6mm x 6mm)
2 SFN (6mm x 6mm)
(2.5k pcs)
2 SFN (3.5mm x 6.5mm)
2 SFN (3.5mm x 6.5mm)
(2.5k pcs)
6 TDFN-EP* (2.5k pcs)
3x3 UCSPR (2.5k pcs)
3x3 UCSPR (10k pcs)
Features
1

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DS2431 Summary of contents

Page 1

... EEPROM memory special feature, the four memory pages can individually be write protected or put in EPROM-emulation mode, where bits can only be changed from state. The DS2431 communi- cates over the single-conductor 1-Wire bus. The commu- nication follows the standard 1-Wire protocol. Each device has its own unalterable and unique 64-bit ROM registration number that is factory lasered into the chip ...

Page 2

... Storage Temperature Range .............................-55°C to +125°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...

Page 3

... Note 12: Applies to a single device attached to a 1-Wire line. Note 13: The earliest recognition of a negative edge is possible at t Note 14: Defines maximum possible bit rate. Equal to t Note 15: Interval after t during which a bus master is guaranteed to sample a logic there is a DS2431 present. RSTL Minimum limit maximum limit is t PDHMAX Note 16: Numbers in bold are not in compliance with legacy 1-Wire product standards ...

Page 4

... OVERDRIVE SPEED (μs) MAX MIN MAX (undefined) 7 (undefined) (undefined 240 8 24 120 the system is close to V PUP PUPMIN DS2431 VALUES STANDARD SPEED OVERDRIVE SPEED (μs) (μs) MIN MAX MIN 65* (undefined) 8* (undefined) 480 640 240 8 60 120 6 ...

Page 5

... The DS2431 combines 1024 bits of EEPROM, an 8-byte register/control page with user read/write bytes, and a fully featured 1-Wire interface in a single chip. Each DS2431 has its own 64-bit ROM registration number that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability. ...

Page 6

... DATA MEMORY, REGISTER PAGE 48-BIT SERIAL NUMBER LSB Each DS2431 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits. ...

Page 7

... Data memory and registers are located in a linear address space, as shown in Figure 5. The data memo- ry and the registers have unrestricted read access. The DS2431 EEPROM array consists of 18 rows of 8 bytes each. The first 16 rows are divided equally into four memory pages (32 bytes each). These four pages are the primary data memory ...

Page 8

... TA2, and E/S (Figure 6). These registers are common to many other 1-Wire devices but operate slightly differ- ently with the DS2431. Registers TA1 and TA2 must be loaded with the target address to which the data is writ- ten or from which data is read. Register E read- only transfer-status register used to verify data integrity with write commands ...

Page 9

... Writing with Verification To write data to the DS2431, the scratchpad must be used as intermediate storage. First, the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. Note that Copy Scratchpad commands must be performed on 8-byte boundaries, i.e., the three LSBs of the target address (T2, T1, T0) must be equal to 000b ...

Page 10

... THE BITWISE LOGICAL N BYTE COUNTER AND OF THE TRANSMITTED BYTE AND THE DATA BYTE FROM THE TARGETED ADDRESS INTO THE SCRATCHPAD. N BUS MASTER Rx CRC-16 OF COMMAND, ADDRESS, E/S BYTE, AND DATA BYTES AS SENT BY THE DS2431 N BUS MASTER MASTER Tx RESET? Rx "1"s AAh TO FIGURE E[2:0]? ...

Page 11

... DATA TO ADDRESS DS2431 Tx "0" BUS MASTER Rx "1"s Y MASTER Tx RESET? N DS2431 Tx "1" N MASTER Tx RESET 1-Wire IDLE HIGH FOR POWER. DS2431 SETS MEMORY ADDRESS = (T[15:0]) BUS MASTER Rx DATA BYTE FROM MEMORY ADDRESS Y BUS MASTER MASTER Tx RESET? Rx "1" MASTER Tx RESET? Y ADDRESS < ...

Page 12

... Bus System The 1-Wire bus is a system that has a single bus mas- ter and one or more slaves. In all instances the DS2431 is a slave device. The bus master is typically a micro- controller. The discussion of this bus system is broken down into three topics: hardware configuration, trans- action sequence, and 1-Wire signaling (signal types and timing) ...

Page 13

... The presence pulse lets the bus master know that the DS2431 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. 1-Wire ROM Function ...

Page 14

... COMMAND DS2431 Tx BIT 0 MASTER Tx BIT 0 DS2431 Tx BIT 0 MASTER Tx BIT BIT 0 MATCH? BIT 0 MATCH DS2431 Tx BIT 1 MASTER Tx BIT 1 DS2431 Tx BIT 1 MASTER Tx BIT BIT 1 MATCH? BIT 1 MATCH DS2431 Tx BIT 63 MASTER Tx BIT 63 DS2431 Tx BIT 63 MASTER Tx BIT ...

Page 15

TO FIGURE 9a FROM FIGURE 9a COMMAND? FROM FIGURE 9a TO FIGURE 9a Figure 9b. ROM Functions Flowchart (continued) ______________________________________________________________________________________ 1024-Bit, 1-Wire EEPROM A5h 3Ch N N RESUME OVERDRIVE- OVERDRIVE- SKIP ROM? MATCH ROM ...

Page 16

... Figure 10 shows the initialization sequence required to begin any communication with the DS2431. A reset pulse followed by a presence pulse indicates that the DS2431 is ready to receive data, given the correct ROM and memory function command. If the bus master uses slew-rate control on the falling edge, it must pull down ...

Page 17

... When responding with a 1, the DS2431 does not hold the data line low at all, and the voltage starts rising as soon as t The sum of t ...

Page 18

... WRITE-ZERO TIME SLOT V PUP V IHMASTER ILMAX RESISTOR READ-DATA TIME SLOT PUP V IHMASTER ILMAX RESISTOR Figure 11. Read/Write Timing Diagrams 18 ______________________________________________________________________________________ ε t SLOT MASTER t W0L t SLOT MASTER t MSR MASTER SAMPLING WINDOW δ t SLOT MASTER ε t REC t REC DS2431 ...

Page 19

... In contrast to the 8-bit CRC, the 16-bit CRC is always communicated in the inverted form. A CRC generator inside the DS2431 chip (Figure 13) calculates a new 16- bit CRC, as shown in the command flowchart (Figure 7). The bus master compares the CRC value read from the ...

Page 20

... Figure 13. CRC-16 Hardware Description and Polynomial by the bus master. The DS2431 transmits this CRC only if E[2:0] = 111b. With the Read Scratchpad command, the CRC is gen- erated by first clearing the CRC generator and then shifting in the command code, the target addresses Command-Specific 1-Wire Communication Protocol— ...

Page 21

Command-Specific 1-Wire Communication Protocol—Color Codes Master to Slave Slave to Master Write Scratchpad (Cannot Fail) RST PD Select WS TA <8–T[2:0] bytes> CRC-16 FF Loop Read Scratchpad (Cannot Fail) RST PD Select RS TA-E/S <8–T[2:0] bytes> CRC-16 FF Loop Copy ...

Page 22

... ______________________________________________________________________________________ With only a single DS2431 connected to the bus mas- ter, the communication looks like this: DATA (LSB FIRST) (Reset) Reset pulse (Presence) Presence pulse CCh Issue “Skip ROM” command 0Fh Issue “Write Scratchpad” command ...

Page 23

... MORE INFORMATION, REFER TO APPLICATION NOTE 4132: ATTACHMENT METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE. ______________________________________________________________________________________ 1024-Bit, 1-Wire EEPROM TOP VIEW TOP VIEW GND N.C. N.C. N. DS2431 GND N.C. N.C. UCSPR *EXPOSED PAD BOTTOM VIEW DS2431GA (3.5mm Pin Configurations DS2431 + N.C. *EP TDFN × (3mm 3mm) GND SFN × × 6.5mm 0.75mm) 23 ...

Page 24

EEPROM 24 ______________________________________________________________________________________ SFN Package Orientation on Tape and Reel USER DIRECTION OF FEED LEADS FACE UP IN ORIENTATION SHOWN ABOVE. SFN × × (6mm 6mm 0.9mm) USER DIRECTION OF FEED LEADS FACE UP IN ORIENTATION SHOWN ABOVE. ...

Page 25

... For the latest package outline information and land patterns (footprints www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. ...

Page 26

... Updated Memory Function Example table Added CSP package outline drawing number to Pin Configuration Changed V TL(MIN) In the Absolute Maximum Ratings, changed storage temp to -55°C to +125°C; in the Electrical Characteristics table, changed V 3 122106 to 40 years min at 85°C; added note to retention spec: “EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated temperatures is not recommended ...

Page 27

... Pin Configurations, and Package Information table Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...

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