DS2432 Maxim, DS2432 Datasheet - Page 2

• Manufacturer Part Number: DS2432
• Description: The DS2432 combines 1024 bits of EEPROM, a 64-bit secret, an 8-byte register/control page with up to five user read/write bytes, a 512-bit SHA-1 engine, and a fully-featured 1-Wire interface in a single chip
• Manufacturer: Maxim

ABRIDGED DATA SHEET
DS2432
DESCRIPTION
The DS2432 combines 1024 bits of EEPROM, a 64-bit secret, an 8-byte register/control page with up to
five user read/write bytes, a 512-bit SHA-1 engine, and a fully-featured 1-Wire interface in a single chip.
Each DS2432 has its own 64-bit ROM registration number that is factory lasered into the chip to provide
a guaranteed unique identity for absolute traceability. Data is transferred serially via the 1-Wire protocol,
which requires only a single data lead and a ground return. The DS2432 has an additional memory area
called the scratchpad that acts as a buffer when writing to the main memory, the register page or when
installing a new secret. Data is first written to the scratchpad from where it can be read back. After the
data has been verified, a copy scratchpad command will transfer the data to its final memory location,
provided that the DS2432 receives a matching 160-Bit MAC. The computation of the MAC involves the
secret and additional data stored in the DS2432 including the device’s registration number. Only a new
secret can be loaded without providing a MAC. The SHA-1 engine can also be activated to compute
160-bit message authentication codes (MAC) when reading a memory page or to compute a new secret,
instead of loading it. Applications of the DS2432 include intellectual property security, after-market
management of consumables, and tamper-proof data carriers.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS2432. The DS2432 has five main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3)
four 32-byte pages of EEPROM, 4) 64-bit register page, 5) 64-bit Secrets Memory, and 6) a 512-bit
SHA-1 Engine (SHA = Secure Hash Algorithm). The hierarchical structure of the 1-Wire protocol is
shown in Figure 2. The bus master must first provide one of the seven ROM Function Commands, 1)
Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume Communication, 6) Overdrive-
Skip ROM or 7) Overdrive-Match ROM. Upon completion of an Overdrive ROM command byte
executed at regular speed, the device will enter Overdrive mode where all subsequent communication
occurs at a higher speed. The protocol required for these ROM function commands is described in Figure
9. After a ROM function command is successfully executed, the memory and SHA-1 functions become
accessible and the master may provide any one of the seven memory function commands. The protocol
*
for these memory function commands is described in Figure 7
. All data is read and written least
significant bit first.
*
For Figure 7, refer to the full version of the data sheet.
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