DS28EC20 Maxim, DS28EC20 Datasheet - Page 12

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DS28EC20

Manufacturer Part Number
DS28EC20
Description
The DS28EC20 is a 20480-bit, 1-Wire® EEPROM organized as 80 memory pages of 256 bits each
Manufacturer
Maxim
Datasheet

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Figure 7-1. Memory Function Flowchart
Bus Master
RX “1”s
DS28EC20
Increments
Scratchpad
Offset
TA1 (T[7:0]), TA2 (T[15:8])
N
Bus Master TX EEPROM
DS28EC20 sets (E[4:0]) =
DS28EC20 sets Scratch-
N
Bus Master TX Memory
Data Bytes as they were
of Command, Address,
sent by the bus master
DS28EC20 TX CRC16
Array Target Address
To Scratchpad Offset
pad Offset = (T[4:0]),
Master TX Data Byte
Function Command
Clears PF, AA, BS
Scratchpad Offset
Scrpad. Offset
Write Scratch-
TX Reset ?
= 11111b?
TX Reset?
Master
Master
pad ?
0Fh
N
Y
Y
Y
Flow Chart (Figure 9)
To ROM Functions
N
12 of 27
Y
Note: The PF Flag is set upon power-
on reset. It is cleared only if a com-
plete 16-bit target address is trans-
mitted. Sending less than 16 bits for
the target address sets the PF flag.
If the memory is write-protected, the
DS28EC20 copies the data byte from
the target address into the scratchpad.
If the memory is in EPROM mode, the
DS28EC20 stores the bitwise logical
AND of the transmitted byte and the
data byte from the targeted address
into the scratchpad.
Partial
Byte ?
PF = 1
From ROM Functions
Flow Chart (Figure 9)
Y
N
DS28EC20: 20Kb 1-Wire EEPROM
From Figure 7,
To Figure 7,
2
2
nd
nd
Part
Part

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