DS1374 Maxim, DS1374 Datasheet - Page 10

• Manufacturer Part Number: DS1374
• Description: The DS1374 is a 32-bit binary counter designed to continuously count time in seconds
• Manufacturer: Maxim

I
Trickle Charger and Reset Input/Output
The power-control function is provided by a precise,
temperature-compensated voltage reference and a
comparator circuit that monitors the V
device is fully accessible and data can be written and
read when V
V
blocked from any access. If V
the device power is switched from V
when V
V
V
ters are maintained from the V
is returned to nominal levels (Table 1). After V
returns above V
after RST goes high (Figure 1).
Table 3. Address Map
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied.
10
Table 2. Power Control
ADDRESS
BACKUP
BACKUP
CC
V
2
V
V
V
CC
CC
CC
CC
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
C, 32-Bit Binary Counter Watchdog RTC with
SUPPLY CONDITION
falls below V
____________________________________________________________________
< V
< V
> V
> V
CC
PF
PF
PF
PF
, the device power is switched from V
when V
, V
, V
, V
, V
drops below V
CC
CC
CC
CC
CC
EOSC
BIT 7
TCS3
OSF
< V
> V
< V
> V
PF
is greater than V
CC
BACKPUP
PF
, read and write access is allowed
BACKUP
BACKUP
BACKUP
, the internal clock registers are
drops below V
WACE
BIT 6
TCS2
0
PF
READ/WRITE
PF
. If V
BACKUP
ACCESS
Power Control
WD/ALM
is less than V
Yes
Yes
BIT 5
TCS1
No
No
PF
0
PF
BACKUP
. However, when
source until V
CC
is greater than
WD/ALM Counter Byte 0
WD/ALM Counter Byte 1
WD/ALM Counter Byte 2
CC
TOD Counter Byte 0
TOD Counter Byte 1
TOD Counter Byte 2
TOD Counter Byte 3
BBSQW
to V
. The regis-
BIT 4
TCS0
POWERED
level. The
V
0
BACKUP
BACKUP
BACKUP
V
V
V
BY
CC
CC
CC
CC
CC
CC
WDSTR
to
BIT 3
DS1
,
0
Table 3 shows the address map for the DS1374 regis-
ters. During a multibyte access, the address pointer
wraps around to location 00h when it reaches the end of
the register space (08h). On an I
address pointer incrementing to location 00h, the current
time is transferred to a second set of registers. These
secondary registers read the time information, while the
clock continues to run. This eliminates the need to reread
the registers in case of an update of the main registers
during a read.
The time-of-day counter is a 32-bit up counter that
increments once per second when the oscillator is run-
ning. The contents can be read or written by accessing
the address range 00h–03h. When the counter is read,
the current time of day is latched into a register, which
is output on the serial data line while the counter contin-
ues to increment.
Note: Writing to any TOD register will reset the 1Hz
square wave output.
BIT 2
RS2
DS0
0
ROUT1
BIT 1
RS1
0
ROUT0
BIT 0
Time-of-Day Counter
AIE
AF
Watchdog/Alarm Counter
Watchdog/Alarm Counter
Watchdog/Alarm Counter
Address Map
2
Time-of-Day Counter
Time-of-Day Counter
Time-of-Day Counter
Time-of-Day Counter
C START, STOP, or
Trickle Charger
FUNCTION
Control
Status