DS1388 Maxim, DS1388 Datasheet
DS1388
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DS1388 Summary of contents
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... SDA RPU = t ______________________________________________ Maxim Integrated Products Features 2 C Interface Ordering Information TEMP RANGE PIN-PACKAGE -40°C to +85° (150 mils) DS1388-5 -40°C to +85° (150 mils) DS138833 -40°C to +85° (150 mils) DS1388-3 Typical Operating Circuit CRYSTAL ...
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... Lead Temperature (soldering, 10s) .................................+260° (Note 1) ......40°C/W Soldering Temperature (reflow) .......................................+260°C JC CONDITIONS DS1388Z-5 V (Note 3) DS1388Z-33 CC DS1388Z-3 V (Note (Note (Note 3) DS1388Z-5 V (Note 3) DS1388Z-33 PF DS1388Z-3 CONDITIONS R1 (Notes (Note 6) R3 (Note (Note 8) LORST OLDOUT MIN TYP MAX UNITS 4 ...
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... V OLSIR CC OL 1.3V < V < 1.8V 0 DS1388Z-5 I (Note 9) DS1388Z-33 CCER DS1388Z-3 DS1388Z-5 I (Note 9) DS1388Z-33 CCEW DS1388Z-3 DS1388Z-5 I (Note 10) DS1388Z-33 CCS DS1388Z +25°C (guaranteed by design -40°C to +85°C (guaranteed by A design) CONDITIONS (Note 11) BACKUP (Note 11) _____________________________________________________________________ MIN TYP MAX 3 ...
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I C RTC/Supervisor with Trickle Charger and 512 Bytes EEPROM AC ELECTRICAL CHARACTERISTICS ( -40°C to +85°C, unless otherwise noted.) (Note 2) CC CC(MIN) CC(MAX) A PARAMETER SYMBOL SCL Clock Frequency Bus ...
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I C RTC/Supervisor with Trickle Charger POWER-UP/POWER-DOWN CHARACTERISTICS (T = -40°C to +85°C) (Note 2) (Figures PARAMETER V Detect to Recognize Inputs CC (V Rising Fall Time PF(MAX) PF(MIN) V ...
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... Note 13: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V to bridge the undefined region of the falling edge of SCL. Note 14: The maximum t need only be met if the device does not stretch the LOW period (t HD:DAT Note 15: A fast-mode device can be used in a standard-mode system, but the requirement t is automatically the case if the device does not stretch the LOW period of the SCL signal ...
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I C RTC/Supervisor with Trickle Charger (V = +3.3V +25°C, unless otherwise noted SUPPLY CURRENT VOLTAGE BACKUP vs. V BACKUP 500 450 400 350 300 250 1.3 1.7 2.1 2.5 ...
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... No external pullup resistors should be connected. If the CC BLOCK 0 CLOCK AND CALENDAR REGISTERS WATCHDOG TIMER STATUS CONTROL/ TRICKLE Pin Description ) of 6.0pF. Pin X1 is the input to the L relative to the the RST exceeds V , for RST delay. RST Block Diagram BLOCK 1 BLOCK 2 EEPROM EEPROM EEPROM INTERFACE DS1388 ...
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... The 2 device is accessed through serial interface. The DS1388 operates as a slave device on the I Access is obtained by implementing a START condition and providing a device identification code followed by data. Subsequent registers can be accessed sequen- tially until a STOP condition is executed. See the Block Diagram , which shows the main elements of the serial real-time clock ...
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... Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clock s for detailed information. Address Map Figure 4 shows the address map for the DS1388. The memory map is divided into three blocks. The memory block accessed is determined by the value of the block address bits in the slave address byte. The timekeep- ing registers reside in block 0h ...
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... Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined oper- ation. The DS1388 can be run in either 12-hour or 24- hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected ...
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... Access is inhibited whenever RST is low. The DS1388 provides for a pushbutton switch to be connected to the RST output pin. When the DS1388 is not in a reset cycle, it continuously monitors the RST signal for a low-going edge edge is detected, the part debounces the switch by pulling the RST pin low and inhibits read/write access ...
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... Control Register (00Ch) Bit 7: Enable Oscillator (EOSC). When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is stopped when the DS1388 switches to battery power. This setting can be used to conserve battery power when timekeeping operation is not required. This bit is cleared (logic 0) when power is first applied. When the ...
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... The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and gener- ates the START and STOP conditions. The DS1388 14 ____________________________________________________________________ BIT 3 ...
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... The master device must generate an extra clock pulse, which is associated with this acknowledge bit. The DS1388 does not generate any acknowledge bits if access to the EEPROM is attempted during an internal pro- gramming cycle. ...
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... START condition from the master device. The slave address byte consists of a 4-bit control code. For the DS1388, this is set as 1101 binary for read and write operations. The next three bits of the slave address byte are the block select bits (B2, B1, B0 always logic 0 for the DS1388 ...
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... Then the master issues the slave address byte again but with the R/W bit set to 1. The DS1388 then issues an acknowledge and transmits the 8-bit data byte. The master issues a NACK followed by a STOP condition, and the DS1388 discontinues transmission ...
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... MASTER TO SLAVE SLAVE TO MASTER For the latest package outline information and land patterns www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status ...
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... Added the package code and land pattern no. to the Package Information table. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...