DS1391 Maxim, DS1391 Datasheet
DS1391
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DS1391 Summary of contents
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... Reset Output/Debounced Input (DS1391/DS1393) ♦ Separate SQW and INT Output (DS1392) ♦ Trickle-Charge Capability ♦ SPI Supports Modes 0 and 2 (DS1394) ♦ SPI Supports Modes 1 and 3 (DS1390/DS1391) ♦ 3-Wire Interface (DS1392/DS1393) ♦ 4MHz at 3.0V and 3.3V ♦ 1MHz at 1.8V ♦ Three Operating Voltages: 1.8V ±5%, 3.0V ±10%, and 2.97 to 5.5V (DS1394: 3.3V ± ...
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... I/O Leakage RST Pin I/O Leakage I LORST DOUT Logic 1 Output I OHDOUT DOUT Logic 0 Output I OHDOUT Logic 0 Output (DS1390/DS1393/DS1394 I SQW/INT; DS1392 SQW, INT; DS1391/DS1393 RST) V Active Supply Current CC (Note 10) 2 _____________________________________________________________________ Storage Temperature Range .............................-55°C to +125°C Soldering Temperature...........................Refer to the IPC/JEDEC + 0.3V) CC CONDITIONS DS139x-33 V ...
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Low-Voltage SPI/3-Wire RTCs with RECOMMENDED DC OPERATING CONDITIONS (continued -40°C to +85°C, unless otherwise noted. Typical values are at nominal supply voltage and T CC CC(MIN) CC(MAX) A unless otherwise noted.) (Note ...
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger SCLK CDH t DC W/R DIN DOUT CPHA = 1 NOTE: SCLK CAN BE EITHER POLARITY SHOWN FOR CPOL = 1. Figure 1a. Timing Diagram—SPI Read ...
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Low-Voltage SPI/3-Wire RTCs with CPHA = SCLK t CDH t DC DIN W/R WRITE ADDRESS BYTE DOUT NOTE: SCLK CAN BE EITHER POLARITY SHOWN FOR CPOL = 1. Figure 2a. Timing Diagram—SPI ...
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger AC ELECTRICAL CHARACTERISTICS—3-WIRE INTERFACE ( -40°C to +85°C.) (Note 1) (Figures CC(MIN) CC(MAX) A PARAMETER SYMBOL SCLK Frequency (Note 13) f Data to SCLK ...
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Low-Voltage SPI/3-Wire RTCs with SCLK CDH t DC I/O A0 WRITE ADDRESS BYTE Figure 3. Timing Diagram—3-Wire Read Transfer SCLK CDH t DC I/O A0 WRITE ...
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger POWER-UP/POWER-DOWN CHARACTERISTICS (T = -40°C to +85°C) (Figures PARAMETER SYMBOL V Detect to Recognize Inputs CC (V Rising Fall Time PF(MAX) V PF(MIN) V Rise Time; ...
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... Note 8: Note 9: The RST pin has an internal 50kΩ (typ) pullup resistor to V Note 10: I —SCLK clocking at max frequency = 4MHz for 3V and 3.3V versions; 1MHz for 1.8V version; RST (DS1391/DS1393) CCA inactive. Outputs are open. Note 11: Specified with bus inactive. Note 12: Measured with a 32.768kHz crystal attached to X1 and X2. Typical values measured at +25°C and 3.0V Note 13: With 50pF load ...
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger (V = +3.3V +25°C, unless otherwise noted vs BBSQ1 = 0 BACKUP BACKUP 600 550 500 450 400 350 300 1.3 1.7 2.1 2.5 2.9 3.3 3.7 ...
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... Low-Voltage SPI/3-Wire RTCs with PIN DS1390/ DS1391 DS1392 DS1393 DS1394 — — — — — — — — 6 — — 9 — — — — — — ...
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... Address and data are transferred seri- ally through a 4-wire SPI interface for the DS1390 and DS1391 and through a 3-wire interface for the DS1392, DS1393, and DS1394. The DS1390/DS1391 operate as a slave device on the SPI serial bus. The DS1392/DS1393 operate using a 3-wire synchronous serial bus ...
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... PF * The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Maxim Real-Time Clocks for addi- tional specifications. The accuracy of the clock is dependent upon the accu- POWERED BY racy of the crystal and the accuracy of the match ...
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... During a multibyte access, when the address pointer reaches 0Fh, it wraps around to location 00h. On the falling edge of the CS pin (DS1390/DS1391/DS1394) or the rising edge of CE (DS1392/DS1393), the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run ...
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... Trickle Charger BIT 1 BIT 0 FUNCTION RANGE 1–12 + Alarm Hours AM/PM 00–23 BCD Alarm Day 1–7 BCD Alarm Date 01–31 BCD 0 AIE DS1390/93/94 Control 0 X DS1391 0 AIE DS1392 0 AF Status Trickle ROUT1 ROUT0 Charger and first applied. CC BACKUP — — 15 ...
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... RST The DS1391/DS1393 provide for a pushbutton switch to be connected to the RST output pin. When the DS1391/DS1393 are not in a reset cycle, it continuously monitors the RST signal for a low-going edge edge is detected, the part debounces the switch by pulling the RST pin low and inhibits read/write access. ...
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... AIE bit is set to logic 0 or INTCN is set to logic 0, the AF bit does not initiate the SQW/INT signal. The AIE bit is disabled (logic 0) when power is first applied. BIT 4 BIT ____________________________________________________________________ Trickle Charger BIT 2 BIT 1 BIT 0 INTCN 0 Control Register (0D/8Dh) (DS1391 Only) BIT 2 BIT 1 BIT AIE X 17 ...
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger BIT 7 BIT 6 BIT 5 EOSC 0 BBSQI The INTCN bit used in the DS1390/DS1393/DS1394 becomes the SQW pin-enable bit in the DS1392. This BIT 7 BIT 6 BIT 5 OSF 0 Bit ...
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... CPOL is the clock-polarity bit set in the control register of the host microprocessor. ** SDO remains at high-Z until 8 bits of data are ready to be shifted out during a read. The user determines diode and resistor selection according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following exam- ple ...
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... Data transfers can occur one byte at a time or in multi- ple-byte burst mode. After CS is driven low, an address is written to the DS1390/DS1391/DS1394. After the address, one or more data bytes can be written or read. For a single-byte transfer, one byte is read or writ- ten and then CS is driven high ...
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Low-Voltage SPI/3-Wire RTCs with CS SCLK (MODE 0) SCLK (MODE 1) DIN W DOUT Figure 10. SPI Single-Byte Write CS SCLK (MODE 0) SCLK (MODE 1) DIN W HIGH IMPEDANCE DOUT Figure 11. SPI ...
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger CS SCLK DIN WRITE ADDRESS BYTE DIN ADDRESS BYTE READ DOUT HIGH-IMPEDANCE Figure 12. SPI Multiple-Byte Burst Transfer CE SCLK I Figure 13. 3-Wire Single-Byte Read CE SCLK I/O A1 ...
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... Serial-Data Bus The DS1392/DS1393 provide a 3-wire serial-data bus, and support both single-byte and multiple-byte data transfers for maximum flexibility. The I/O pin is the seri- al-data input/output pin. The CE input is used to initiate and terminate a data transfer. The SCLK pin is used to synchronize data movement between the master (microcontroller) and the slave (DS1392/DS1393) devices ...
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... SQW/INT SCLK BACKUP 7 4 DOUT DIN GND SQW SCLK BACKUP 7 I INT 5 GND Pin Configurations RST DS1391 8 SCLK 7 DOUT 6 DIN μSOP SQW/INT DS1393 8 SCLK 7 I/O 6 RST μSOP ...
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... SQW CPU INT V BACKUP RST PACKAGE CODE — ____________________________________________________________________ Trickle Charger Typical Operating Circuits CRYSTAL SCLK DOUT DS1391 V BACKUP DIN RST GND CRYSTAL SQW/INT SCLK DS1393 I/O V BACKUP RST GND Package Information DOCUMENT NO. 21-0061 ...
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... Added DS1390U-33/V+ to the Ordering Information table. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © ...