DS1673 Maxim, DS1673 Datasheet - Page 7

• Manufacturer Part Number: DS1673
• Description: The DS1673 portable system controller is a circuit that incorporates many of the functions necessary for low-power portable products integrated into one chip
• Manufacturer: Maxim

STATUS REGISTER
CU (Conversion Update In Progress). When this bit is a 1, an update to the ADC Register (register
0Eh) will occur within 488s. When this bit is a 0, an update to the ADC Register will not occur for at
least 244s.
LOBAT (Low Battery Flag). This bit reflects the status of the backup power source connected to the
V
LOBAT is set to a logic 1.
IRQF (Interrupt Request Flag). A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the time of day Alarm registers. If the AIE bit is also a logic 1, the INT pin will go
high. IRQF is cleared by reading or writing to any of the alarm registers.
POWER-UP DEFAULT STATES
These bits are set to a one upon initial power-up: EOSC , TD1 and TD0. These bits are cleared upon
initial power-up: WP, AIS1, and AIS0.
NONVOLATILE SRAM CONTROLLER
The DS1673 provides automatic backup and write protection for external SRAM. This function is
provided by gating the chip enable signals and by providing a constant power supply through the V
pin. The DS1673 was specifically designed with the Intel 80186 and 386EX microprocessors in mind. As
such, the DS1673 has the capability to provide access to the external SRAM in either byte-wide or word-
wide format. This capability is provided by the chip enable scheme. Three input signals and two output
signals are used for enabling the external SRAM(s) (see Figure 4).
enable), and
these pins.
The DS1673 nonvolatilizes the external SRAM(s) by write-protecting the SRAM(s) and by providing a
back-up power supply in the absence of V
are prohibited by forcing
power-up, access is prohibited until the end of t
EXTERNAL SRAM CHIP ENABLE Table 3
CEOL
BAT
CEI
BIT 7
0
0
0
0
1
CU
pin. When V
(chip enable low) and the
BHE
BLE
X
0
0
1
1
LOBAT
BIT 6
(byte low enable) are used for enabling either one or two external SRAMs through the
BAT
BLE
is greater than 2.5V, LOBAT is set to a logic 0. When V
X
0
1
0
1
CEOL
BIT 5
0
CEOL
and
0
1
0
1
1
CEOH
CEOH
CEOH
(chip enable high) outputs. Table 3 illustrates the function of
CC
BIT 4
. When V
0
0
1
1
1
0
high regardless of the level of
RPU
.
Word transfer
Byte transfer in upper half of data bus (D15-D8)
Byte transfer in lower half of data bus (D7-D0)
External SRAMs disabled
External SRAMs disabled
7 of 18
CC
BIT 3
falls below V
0
CEI
BIT 2
PF
0
FUNCTION
(chip enable in),
, access to the external SRAM(s)
CEI
,
BIT 1
BLE
BAT
0
is less than 2.3V,
, and
BHE
BHE
BIT 0
(byte high
IRQF
. Upon
DS1673
CCO