DS1682 Maxim, DS1682 Datasheet - Page 11
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DS1682
Manufacturer Part Number
DS1682
Description
The DS1682 is an integrated elapsed-time recorder containing a factory-calibrated, temperature-compensated RC time base that eliminates the need for an external crystal
Manufacturer
Maxim
Datasheet
1.DS1682.pdf
(14 pages)
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The DS1682 can operate in the following two modes:
Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After
each byte is received, the receiver transmits an acknowledge bit. START and STOP conditions are
recognized as the beginning and end of a serial transfer. The slave address byte is the first byte received
after the master generates a START condition. The address byte contains the 7-bit DS1682 address,
which is 1101011, followed by the direction bit (R/W). The second byte from the master is the register
address. This sets the register pointer. The master then transmits each byte of data, with the DS1682
acknowledging each byte received. The register pointer increments after each byte is written. The master
generates a STOP condition to terminate the data write (Figure 7).
Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver
mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data
is transmitted on SDA by the DS1682 while the serial clock is input on SCL. The slave address byte is the
first byte received after the master generates a START condition. The address byte contains the 7-bit
DS1682 address, followed by the direction bit (R/W). After receiving a valid slave address byte and
direction bit, the DS1682 generates an acknowledge on the SDA line. The DS1682 begins to transmit
data on each SCL pulse starting with the register address pointed to by the register pointer. As the master
reads each byte, it must generate an acknowledge. The register pointer increments after each byte is read.
The DS1682 must receive a “not acknowledge” on the last byte to end a read (Figure 8).
Figure 7. Data Write—Slave Receiver Mode
Figure 8. Data Read—Slave Transmitter Mode
R/W –READ/WRITE OR DIRECTION BIT
S
S—START
A—- ACKNOWLEDGE
P—- STOP
/A — NOT ACKNOWLEDGE
R/W — READ/WRITE OR DIRECTION BIT
S
S–START
A –ACKNOWLEDGE
P– STOP
1101011
ADDRESS
1101011
ADDRESS
SLAVE
SLAVE
R/W
R/W
1 A
0 A
XXXXXXXX
XXXXXXXX
DATA (n)
REGISTER
ADDRESS
A
A
XXXXXXXX
XXXXXXXX
DATA (n + 1)
DATA (n)
11 of 14
A
A
(X + 1 BYTES + ACKNOWLEDGE)
(X + 1 BYTES + ACKNOWLEDGE)
XXXXXXXX
XXXXXXXX
DATA (n + 1)
DATA (n + 2)
DATA TRANSFERRED
DATA TRANSFERRED
A
A
XXXXXXXX /A
XXXXXXXX
DATA (n + x)
DATA (n + x)
P