DS83C520 Maxim, DS83C520 Datasheet
DS83C520
Related parts for DS83C520
DS83C520 Summary of contents
Page 1
... Interrupt Sources with Six External Available in 40-pin PDIP, 44-Pin PLCC, 44-Pin TQFP, and 40-Pin Windowed CERDIP Factory Mask DS83C520 or EPROM (OTP) DS87C520 The High-Speed Microcontroller User’s Guide must be used in conjunction with this data sheet. Download it at: www.maxim-ic.com/microcontrollers. ...
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... DS83C520-QNL+ -40˚C to +85˚C DS83C520-ENL -40˚C to +85˚C DS83C520-ENL+ -40˚C to +85˚C + Denotes a lead(Pb)-free/RoHS-compliant device. * The windowed ceramic DIP package is intrinsically lead(Pb) free. DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers MAX CLOCK PIN-PACKAGE SPEED (MHz Plastic DIP 33 40 Plastic DIP 33 ...
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... The EMI reduction feature allows software to select a reduced emission mode. This disables the ALE signal when it is unneeded. The DS83C520 is a factory mask ROM version of the DS87C520 designed for high-volume, cost- sensitive applications identical in all respects to the DS87C520, except that the 16kB of EPROM is replaced by a user-supplied application program ...
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... DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers NAME V Positive Supply Voltage. +5V CC GND Digital Circuit Ground Reset Input. The RST input pin contains a Schmitt voltage input to recognize external active high Reset inputs. The pin also 4 RST employs an internal pulldown resistor to allow for a combination of wired OR external reset sources ...
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... P1.2 When software writes any port pin, the DS87C520/DS83C520 will activate a strong pulldown that remains on until either written or a reset occurs. Writing a 1 after the port has been at 0 will P1 ...
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... External Data Memory Write Strobe P3.7 P3.7 RD External Data Memory Read Strobe External Access Input, Active Low. Connect to ground to force the DS87C520/DS83C520 to use an external ROM. The internal EA RAM is still accessible as determined by register settings. Connect use internal ROM. CC Not Connected. These pins should not be connected. They are N ...
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... COMPATIBILITY The DS87C520/DS83C520 are fully static CMOS 8051-compatible microcontrollers designed for high performance. In most cases, the DS87C520/DS83C520 can drop into an existing socket for the 8xc51 family to improve the operation significantly. While remaining familiar to 8051 family users, the devices have many new features. In general, software written for existing 8051-based systems works without modification on the DS87C520/DS83C520 ...
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... SPECIAL FUNCTION REGISTERS Special Function Registers (SFRs) control most special features of the DS87C520/DS83C520. This allows the DS87C520/DS83C520 to have many new features but use the same instruction set as the 8051. When writing software to use a new feature, an equate statement defines the SFR to an assembler or compiler ...
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... RCAP2L RCAP2H TL2 TH2 PSW CY AC WDCON SMOD_1 POR ACC — — EIE B — — EIP Note: New functions are in bold. DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers BIT 5 BIT 4 BIT 3 P0.5 P0.4 P0 — — GF1 TF0 TR0 IE1 M1 M0 GATE T2M T1M T0M P1 ...
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... MEMORY RESOURCES Like the 8051, the DS87C520/DS83C520 use three memory areas. The total memory configuration of the DS87C520/DS83C520 is 16kB of ROM, 1kB of data SRAM and 256 bytes of scratchpad or direct RAM. The 1kB of data space SRAM is read/write accessible and is memory mapped. This on-chip SRAM is reached by the MOVX instruction ...
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... DEFAULT = 16kB DATA MEMORY ACCESS Unlike many 8051 derivatives, the DS87C520/DS83C520 contain on-chip data memory. They also contain the standard 256 bytes of RAM accessed by direct instructions. These areas are separate. The MOVX instruction accesses the on-chip data memory. Although physically on-chip, software treats this area as though it was located off-chip ...
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... When disabled, the 1kB memory area is transparent to the system memory map. Any MOVX directed to the space between 0000h and FFFFh goes to the expanded bus on Ports 0 and 2. This also is the default condition. This default allows the DS87C520/DS83C520 to drop into an existing system that uses these addresses for other hardware and still have full compatibility. ...
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... The timing of block moves of data memory is faster using the Dual Data Pointer (DPTR). The standard 8051 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the DS87C520/DS83C520, this data pointer is called DPTR0, located at SFR addresses 82h and 83h. These are the original locations. Using DPTR requires no modification of standard code. The new DPTR at SFR 84h and 85h is called DPTR1 ...
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... Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU to run software but to use substantially less power. During default operation, the DS87C520/DS83C520 use four clocks per machine cycle. Thus the instruction cycle rate is Clock/4. At 33MHz crystal speed, the instruction cycle speed is 8 ...
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... CRYSTAL-LESS PMM A major component of power consumption in PMM is the crystal amplifier circuit. The DS87C520/DS83C520 allow the user to switch CPU operation to an internal ring oscillator and turn off the crystal amplifier. The CPU would then have a clock source of approximately 2MHz to 4MHz, divided by either 4, 64, or 1024. The ring is not accurate, so software cannot perform precision timing. However, this mode allows an additional saving of between 0 ...
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... To return to a 4-clock rate from PMM, software can simply select the CD1 and CD0 clock control bits to the 4 clocks per cycle state. However, the DS87C520/DS83C520 provide several hardware alternatives for automatic Switchback. If Switchback is enabled, then the device will automatically return to a 4-clock per cycle speed when an interrupt occurs from an enabled, valid external interrupt source ...
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... Crystal/Ring Operation The DS87C520/DS83C520 allow software to choose the clock source as an independent selection from the instruction cycle rate. The user can select crystal-based or ring oscillator-based operation under software control. Power-on reset default is the crystal (or external clock) source. The ring may save power depending on the actual crystal speed ...
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... Status. Serial transmission on serial port 1. SPRA1 STATUS.2 Status. Serial word reception on serial port 1. SPTA0 STATUS.1 Status. Serial transmission on serial port 0. SPRA0 STATUS.0 Status. Serial word reception on serial port 0. DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers FUNCTION . RESET WRITE ACCESS only when X XTUP = 1 and XTOFF = 0 ...
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... Figure 3. Invoking and Clearing PMM DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers ...
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... Internally generated interrupts (timer, serial port, Watchdog) are not useful since they require clocking activity. The DS87C520/DS83C520 provide two enhancements to the Stop mode. As documented below, the device provides a bandgap reference to determine Power-Fail Interrupt and Reset thresholds. The default state is that the bandgap reference is off while in Stop mode ...
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... When ALEOFF = 1, ALE will still toggle during an off-chip MOVX. However, ALE will remain in a static mode when performing on-chip memory access. The default state of ALEOFF = 0 so ALE toggles at a frequency of XTAL/4. DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers STOP MODE WITHOUT RING STARTUP STOP MODE WITH RING STARTUP ...
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... CKCON bit is a logic 1, the DS87C520/DS83C520 use 4 clocks per cycle to generate timer speeds. When the bit the DS87C520/DS83C520 use 12 clocks for timer speeds. The reset condition CKCON.5 selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer 0. ...
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... PFI flag at WDCON.4. A PFI condition sets this bit The flag is independent of the interrupt enable and software must manually clear it. WATCHDOG TIMER To prevent software from losing control, the DS87C520/DS83C520 include a programmable Watchdog Timer. The Watchdog is a free-running timer that sets a flag if allowed to reach a preselected timeout. It can be (re)started by software. ...
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... Watchdog Interrupt using EWDI (EIE.4). The Special Function Register map is shown above. INTERRUPTS The DS87C520/DS83C520 provide 13 interrupt sources with three priority levels. The Power-Fail Interrupt (PFI) has the highest priority. Software can assign high or low priority to other sources. All interrupts that are new to the 8051 family, except for the PFI, have a lower natural priority than the originals ...
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... Increase the voltage Pulse the signal five times for EPROM array and 25 times for encryption table, lock bits, and PROG other EPROM bits, 6) Repeat as many times as necessary. DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers BGS Bandgap Select POR Power-On Reset flag EWT Enable Watchdog Reset ...
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... Table 10 shows the security settings. Note that the programmer cannot directly read the state of the security lock. User software has access to this information as described in the Memory section. DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers PSEN EA/VPP ...
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... Bits Reserved. Program SIGNATURE The Signature bytes identify the product and programming revision to EPROM programmers. This information is at programming addresses 30h, 31h, and 60h. ADDRESS 30h 31h 60h DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers VALUE MEANING DAh Manufacturer 20h Model 01h Extension ...
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... The DS83C520 supports a subset of the EPROM features found on the DS87C520. SECURITY OPTIONS Lock Bits The DS83C520 employs a lock that restricts viewing of the ROM contents. When set, the lock will prevent MOVC instructions in external memory from reading program bytes in internal memory. When locked, the pin is sampled and latched on reset ...
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... DS83C520 ROM VERIFICATION The DS83C520 memory contents can be verified using a standard EPROM programmer. The memory address to be verified is placed on the pins shown in Figure 5, and the programming control pins are set to the levels shown in Table 9. The data at that location is then asserted on port 0. ...
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... Output High Voltage Ports ALE, PSEN -50μA OH Output High Voltage Ports -1.5mA OH Output High Voltage Port 0, 2, ALE, PSEN in Bus Mode Input Low Current Ports 0.45V DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers SYMBOL MIN V 4.5 CC 4.25 V PFW 4.25 4.0 V RST 4 ...
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... This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set to 1. This is only the current required to hold the low level; transitions from I/O pin will also have to overcome the transition current. TYPICAL I vs. FREQUENCY CC DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers SYMBOL MIN ...
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... Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing will change in relation to duty cycle variation. Note 2: Address is driven strongly until ALE falls, and is then held in a weak latch until overdriven externally. DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers 33 MHz SYMBOL MIN ...
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... Stretch memory cycle selection. The following table shows the value of t MCS each Stretch selection. Note 2: Address is driven strongly until ALE falls, and is then held in a weak latch until overdriven externally. DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers VARIABLE CLOCK SYMBOL MIN 1.5t ...
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... Output Data Hold from t Clock Rising Input Data Hold after t Clock Rising Clock Rising Edge to t Input Data Valid DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers MOVX CYCLES 2 machine cycles 3 machine cycles (default) 4 machine cycles 5 machine cycles 6 machine cycles 7 machine cycles 8 machine cycles 9 machine cycles ...
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... EXPLANATION OF AC SYMBOLS In an effort to remain compatible with the original 8051 family, the DS87C520 and DS83C520 specify the same parameters as such devices, using the same symbols. For completeness, the following is an explanation of the symbols. t Time A Address C Clock D Input data H Logic level high ...
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... DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers ...
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... EXTERNAL PROGRAM MEMORY READ CYCLE EXTERNAL DATA MEMORY READ CYCLE DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers t AVLL2 ...
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... EXTERNAL DATA MEMORY WRITE CYCLE DATA MEMORY WRITE WITH STRETCH = 1 DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers ...
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... DATA MEMORY WRITE WITH STRETCH = 2 EXTERNAL CLOCK DRIVE DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers FOUR CYCLE DATA MEMORY WRITE STRETCH VALUE ...
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... SERIAL PORT MODE 0 TIMING SERIAL PORT 0 (SYNCHRONOUS MODE) HIGH SPEED OPERATION SM2=1=>TXD CLOCK=XTAL/4 DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers ...
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... POWER-CYCLE TIMING EPROM PROGRAMMING AND VERIFICATION WAVEFORMS DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers ...
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... PACKAGE INFORMATION For the latest package outline information www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE 44 TQFP C44+3 40 CDIP J40-5 40 PDIP P40+4 44 PLCC Q44+9 DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers DOCUMENT NO. 21-0293 21-0384 21-0044 21-0049 ...
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... AVLL2 1) Added Pb-free/RoHS-compliant part numbers to Ordering Information table. 070505 2) Deleted the “A” from the IPC/JEDEC J-STD-020 specification in the Absolute Maximum Ratings Electrical Characteristics table, added separate specification for DS83C520 V 091605 2) Changed V RST 1) (Page 30) In the Absolute Maximum Ratings table, changed the operating range from 0C to +70C to -40 ...