MAXQ610 Maxim, MAXQ610 Datasheet - Page 13

• Manufacturer Part Number: MAXQ610
• Description: The MAXQ610 is a low-power, 16-bit MAXQ® microcontroller designed for low-power applications including universal remote controls, consumer electronics, and white goods
• Manufacturer: Maxim

Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
The watchdog timer functions as the source of both the
watchdog-timer timeout and the watchdog-timer reset.
The timeout period can be programmed in a range of
2
ed when the timeout period expires if the interrupt is
enabled. All watchdog-timer resets follow the pro-
grammed interrupt timeouts by 512 system clock
cycles. If the watchdog timer is not restarted for another
full interval in this time period, a system reset occurs
when the reset timeout expires. See Table 2.
The dedicated IR timer/counter module simplifies low-
speed IR communication. The IR timer implements two
pins (IRTX and IRRX) for supporting IR transmit and
receive, respectively. The IRTX pin has no correspond-
ing port pin designation, so the standard PD, PO, and
PI port control status bits are not present. However, the
IRTX pin output can be manipulated high or low using
the PWCN.IRTXOUT and PWCN.IRTXOE bits when the
IR timer is not enabled (i.e., IREN = 0).
The IR timer is composed of two separate timing enti-
ties: a carrier generator and a carrier modulator. The
carrier generation module uses the 16-bit IR Carrier
register (IRCA) to define the high and low time of the
carrier through the IR carrier high byte (IRCAH) and IR
carrier low byte (IRCAL). The carrier modulator uses the
IR data bit (IRDATA) and IR Modulator Time register
(IRMT) to determine whether the carrier or the idle con-
dition is present on IRTX.
The IR timer is enabled when the IR enable bit (IREN) is
set to 1. The IR Value register (IRV) defines the begin-
ning value for the carrier modulator. During transmis-
sion, the IRV register is initially loaded with the IRMT
value and begins down counting towards 0000h,
whereas in receive mode it counts upward from the ini-
tial IRV register value. During the receive operation, the
IRV register can be configured to reload with 0000h
when capture occurs on detection of selected edges or
15
WD[1:0]
to 2
00
01
10
11
24
system clock cycles. An interrupt is generat-
16-Bit Microcontroller with Infrared Module
IR Carrier Generation and
______________________________________________________________________________________
WATCHDOG CLOCK
Sysclk/2
Sysclk/2
Sysclk/2
Sysclk/2
Modulation Timer
15
18
21
24
WATCHDOG INTERRUPT TIMEOUT
174.7ms
can be allowed to continue free-running throughout the
receive operation. An overflow occurs when the IR timer
value rolls over from 0FFFFh to 0000h. The IR overflow
flag (IROV) is set to 1 and an interrupt is generated if
enabled (IRIE = 1).
The IRCAH byte defines the carrier high time in terms of
the number of IR input clocks, whereas the IRCAL byte
defines the carrier low time.
During transmission, the IRCA register is latched for
each IRV downcount interval and is sampled along with
the IRTXPOL and IRDATA bits at the beginning of each
new IRV downcount interval so that duty-cycle variation
and frequency shifting is possible from one interval to
the next, which is illustrated in Figure 1.
Figure 2 illustrates the basic carrier generation and its
path to the IRTX output pin. The IR transmit polarity bit
(IRTXPOL) defines the starting/idle state and the carrier
polarity of the IRTX pin when the IR timer is enabled.
During IR transmission (IRMODE = 1), the carrier gener-
ator creates the appropriate carrier waveform, while the
carrier modulator performs the modulation. The carrier
modulation can be performed as a function of carrier
cycles or IRCLK cycles dependent on the setting of the
IRCFME bit. When IRCFME = 0, the IRV downcounter is
clocked by the carrier frequency and thus the modula-
tion is a function of carrier cycles. When IRCFME = 1,
the IRV downcounter is clocked by IRCLK, allowing car-
rier modulation timing with IRCLK resolution.
21.9ms
Carrier Duty Cycle = (IRCAH + 1)/(IRCAH + IRCAL + 2)
2.7ms
1.4s
IR Input Clock (f
Carrier Frequency (f
Carrier High Time = IRCAH + 1
Carrier Low Time = IRCAL + 1
f
IRCLK
/(IRCAH + IRCAL + 2)
Carrier Generation Module
IRCLK
WATCHDOG INTERRUPT (μs)
WATCHDOG RESET AFTER
) = f
CARRIER
SYS
IR Transmission
42.7
42.7
42.7
42.7
/2
IRDIV[1:0]
) =
13