DS5002FP Maxim, DS5002FP Datasheet - Page 8

• Manufacturer Part Number: DS5002FP
• Description: The DS5002FP secure microprocessor chip is a secure version of the DS5001FP 128k soft microprocessor chip
• Manufacturer: Maxim

AC CHARACTERISTICS—BYTE-WIDE ADDRESS/DATA BUS TIMING
(V
Figure 6. Byte-Wide Bus Timing
CC
40
41
42
43
44
45
46
47
48
49
50
51
52
53
#
= 5V ±10%, T
Delay to Byte-Wide Address Valid from CE1 ,
CE2 , or CE1N Low During Op Code Fetch
Pulse Width of CE 1–4, PE 1–4, or CE1N
Byte-Wide Address Hold After CE1 , CE2 , or
CE1N High During Op Code Fetch
Byte-Wide Data Setup to CE1 , CE2 , or CE1N
High During Op Code Fetch
Byte-Wide Data Hold After CE1 , CE2 , or CE1N
High During Op Code Fetch
Byte-Wide Address Hold After CE 1–4, PE 1–4, or
CE1N High During MOVX
Delay from Byte-Wide Address Valid CE 1–4,
PE 1–4, or CE1N Low During MOVX
Byte-Wide Data Setup to CE 1–4, PE 1–4, or
CE1N High During MOVX (Read)
Byte-Wide Data Hold After CE 1–4, PE 1–4, or
CE1N High During MOVX (Read)
Byte-Wide Address Valid to R/ W Active During
MOVX (Write)
Delay from R/ W Low to Valid Data Out During
MOVX (Write)
Valid Data Out Hold Time from CE 1–4, PE 1–4, or
CE1N High
Valid Data Out Hold Time from R/ W High
Write Pulse Width (R/ W Low Time)
A
= 0°C to +70°C.)
PARAMETER
(Figure
6)
8 of 25
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
t
OVCE1H
CE1HOV
t
CE1HPA
CE1LPA
t
RWHDV
RWLPW
AVRWL
RWLDV
CEHDA
DACEH
CEHDV
CEHDV
CELDA
CEPW
1t
1t
4t
2t
4t
4t
3t
1t
6t
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
MIN
20
0
0
0
+ 40
+ 40
- 35
- 20
- 30
- 35
- 35
- 15
- 20
MAX
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns