71M6113 Maxim, 71M6113 Datasheet - Page 4

• Manufacturer Part Number: 71M6113
• Description: The 71M6103/71M6113/71M6201/71M6203/71M6601/71M6603 (71M6xxx) isolated sensor ICs enable Teridian's 4th-generation polyphase-metering 71M654x systems-on-chips (SoCs) to use nonisolating sensors such as resistive shunts without the need for costly and
• Manufacturer: Maxim

When PLL_FAST = 1 in the 71M654x, power pulses generated by the 71M654x arrive every 610.35ns.
The PLL in the 71M6xxx locks to these incoming power pulses. The communication between the
PDS_6xxx_010
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The 71M6103/71M6113/71M6201/71M6203/71M6601/71M6603 (71M6xxx) remote sensor ICs integrate
all functional blocks required to implement an isolated front-end with digital communication capability.
Figure 1
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During normal operation, the SP and SN pins of the 71M6xxx are connected to the pulse transformer.
71M654x and the 71M6xxx is synchronized to the multiplexer frames of the 71M654x. The
communication protocol is Teridian-proprietary, and details are not described in this data sheet. All
aspects of the communication between the 71M654x and the 71M6xxx are managed on the hardware
level and they are completely transparent to the user.
The communication interface can run at two different data rates. Power pulses are generated every
610.35ns if the PLL_FAST register in the 71M654x is set to 1, and every 1.905µs if PLL_FAST is set to 0.
The power pulses are 101.7ns wide with PLL_FAST = 1, and 160ns wide with PLL_FAST = 0.
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71M654X
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Primary
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HARDWARE DESCRIPTION
Preamplifier with a fixed gain
22-bit delta-sigma ADC
ADC voltage reference
Temperature sensor
VCC monitor
Power-on reset circuitry
Bidirectional pulse interface
Active rectifiers for supply-voltage generation from the power pulses provided by the 71M654x
Digital control section providing control registers for the selection of operation modes
FUNCTIONAL DESCRIPTION
shows the 71M6xxx IC block diagram. The chip includes the following:
Secondary
SHUNT
INP
INN
SP
SN
+
+
-
-
GND
PULSEIO
RD_DATA
ACTIVE
RECTI-
PREAMP
FIERS
PLL
VCC
CROSS
© 2008–2011 Teridian Semiconductor Corporation
POWER
RESET
ON
Figure 1: Block Diagram
RESET
WR_DATA
RD_DATA
VDD
RD_CLK
TEST
ADC_CLK
DIGITAL SECTION
ADC
DATA_IN[15:0]
ADC_OUT
VBIAS
VREF
CHOP
BUFFER
BAND
GAP
OTP MEMORY
IBIAS
71M6xxx Data Sheet
TEMP/VCC
MONITOR
VCC
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