DS8005 Maxim, DS8005 Datasheet - Page 10

• Manufacturer Part Number: DS8005
• Description: The DS8005 dual smart card interface is a low-cost, dual analog front-end for an IC card reader interface that needs to communicate with two smart cards in a mutually exclusive fashion
• Manufacturer: Maxim

Smart Card Interface
The voltage supervisor monitors the V
220µs reset pulse (t
device inactive during power-on or power-off of the
V
The IC card interface remains inactive regardless of the
levels on the command lines until duration t
has reached a level higher than V
V
deactivation sequence if the card interface is active.
The card clock signal (CLKA/CLKB) is derived from a
clock signal input to XTAL1 or from a crystal operating
at up to 20MHz connected between XTAL1 and XTAL2.
The output clock frequency of CLK_ is selectable
through inputs CLKDIV1 and CLKDIV2. The CLK signal
frequency can be f
See Table 1 for the frequency generated on the CLK_
signal given the inputs to CLKDIV1 and CLKDIV2.
Note that CLKDIV1 and CLKDIV2 must not be changed
simultaneously; a delay of 10ns minimum between
changes is needed. The minimum duration of any state
of CLK_ is eight periods of XTAL1.
Table 1. Clock Frequency Selection
Figure 2. Voltage Supervisor Behavior
10
DD
DD
supply. See Figure 2.
______________________________________________________________________________________
CLKDIV1
falls below V
(INTERNAL SIGNAL)
0
0
1
1
ALARM
V
DD
TH2
XTAL
W
) is used internally to keep the
, the device executes a card
CLKDIV2
Voltage Supervisor
, f
XTAL
0
1
1
0
Clock Circuitry
/2, f
TH2
XTAL
+ V
POWER ON
/4, or f
DD
t
f
f
f
W
HYS2
W
XTAL
XTAL
XTAL
f
f
XTAL
CLK
supply. A
after V
/8
/4
/2
XTAL
. When
DD
/8.
The frequency change is synchronous: during a transi-
tion of the clock divider, no pulse is shorter than 45% of
the smallest period, and the first and last clock pulses
about the instant of change have the correct width.
When changing the frequency dynamically, the change
is effective for only eight periods of XTAL1 after the
command.
The f
XTAL1. To reach a 45% to 55% duty factor on CLK_,
XTAL1 should have a 48% to 52% duty factor with tran-
sition times less than 5% of the period.
With a crystal, the duty factor on CLK_ can be 45% to
55% depending on the circuit layout and on the crystal
characteristics and frequency. In other cases, the duty
factor on CLK_ is guaranteed between 45% and 55% of
the clock period.
I/O_ and I/OIN are pulled high with an 11kΩ resistor
(I/O_ to V
The first side of the transceiver to receive a falling edge
becomes the master. When a falling edge is detected
(and the master is decided), the detection of falling
edges on the line of the other side is disabled; that side
then becomes a slave. After a time delay t
transistor on the slave side is turned on, thus transmit-
ting the logic 0 present on the master side.
When the master side asserts a logic 1, a p transistor
on the slave side is activated during the time delay t
and then both sides return to their inactive (pulled up)
states. This active pullup provides fast low-to-high tran-
sitions. After the duration of t
depends only on the internal pullup resistor and the
SUPPLY DROPOUT
XTAL
t
CC_
W
duty factor depends on the input signal on
and I/OIN to V
I/O Transceivers
DD
PU
) in the inactive state.
, the output voltage
POWER OFF
V
V
TH2
TH2
+ V
D(EDGE)
HYS2
, an n
PU