DS4550 Maxim, DS4550 Datasheet
DS4550
Related parts for DS4550
DS4550 Summary of contents
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... Rev 0; 9/04 I General Description The DS4550 is a 9-bit, nonvolatile (NV) I/O expander with 64 bytes of NV user memory controlled by either C-compatible serial interface or an IEEE 1149.1 JTAG port. The DS4550 offers a digitally programmable alternative to hardware jumpers and mechanical switches that are being used to control digital logic nodes ...
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... Operating Temperature Range ...........................-40°C to +85°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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I AC ELECTRICAL CHARACTERISTICS-– +2.7V to +5.5V -40°C to +85°C, unless otherwise noted. Timing referenced PARAMETER SYMBOL SCL Clock Frequency Bus Free Time Between Stop and Start Conditions Hold Time (Repeated) Start ...
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I C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory NONVOLATILE MEMORY CHARACTERISTICS (V = +2.7V to +5.5V, unless otherwise noted.) CC PARAMETER SYMBOL EEPROM Writes Note 1: All voltages referenced to ground. Note specified with ...
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+5.0V +25°C; TDI, TDO, TMS pins are no connects, unless otherwise noted SUPPLY CURRENT vs. SUPPLY VOLTAGE 2 I/O0-I/O7 CONTROL BITS = 0 I/O0-I/O7 PULLUPS DISABLED V = SDA = SCL = TCK ...
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I C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory PIN NAME 1 I/O_0 Input/Output 0. Bidirectional I/O pin. 2 I/O_1 Input/Output 1. Bidirectional I/O pin. 3 I/O_2 Input/Output 2. Bidirectional I/O pin. 4 I/O_3 Input/Output 3. Bidirectional I/O ...
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... TDI CONTROL TDO PORT TCK GND Detailed Description The DS4550 contains nine bidirectional, NV, input/out- put (I/O) pins, and a 64-byte EEPROM user memory. The I/O pins and user memory are accessible through 2 either the I C compatible serial bus or the IEEE 1149.1 JTAG interface. Programmable NV I/O Pins ...
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... AC Electrical can be programmed for the I/Os in EEPROM (with SEE = 0) and then once powered up, SEE can be written that the I/Os can be updated periodically in SRAM. The final type of memory present in the DS4550 is standard SRAM. FUNCTION 64 Bytes of General-Purpose User EEPROM. Undefined Address Space for Future Expansion. Reads and writes to this space will have no affect on the device. ...
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... JTAG instructions. The DS4550 also contains some exten- A0 R/W sions to normal JTAG functionality, which allows access to the internal memory. In particular, the DS4550 has READ/WRITE three device-specific test data registers (Memory BIT Address, Memory Read, and Memory Write) and three device-specific instructions (ADDRESS, READ, and WRITE), which provide memory access ...
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I C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Test Access Port (TAP) Controller State Machine The TAP controller is a finite state machine that responds to the logic level at TMS on the rising edge of TCK ...
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... IR state. The falling edge of that same TCK latches the data in the Instruction shift register to the Instruction Register parallel output. Instructions supported by the DS4550 and its respective operational binary codes are shown in SAMPLE/PRELOAD. This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions ...
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... Memory Write test data register during the Shift-DR state. When EEPROM writes occur using the JTAG interface, the DS4550 will write the whole EEP- ROM memory page (8 bytes) even though only a single byte is modified. The unmodified bytes of the page are transparently rewritten to their current values ...
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I Table 3. Boundary Scan Control Bits [33 Bits] CELL NAME NUMBER 32 A2 input 31 A1 input 30 A0 input 29 SCL input 28 SDA input 27 SDA output 26 IO8 pubout 25 IO8 pdbout 24 IO8 input 23 ...
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I C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Table 5. EEPROM Write Cycle STEP TAP STATE Select-IR-Scan Capture-IR Select Address Shift- TCK) Register Exit1-IR Update-IR Select-DR-Scan Capture-DR Load EEPROM Shift- TCK) Address Exit1-DR ...
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I Bit Read: At the end a write operation, the master must release the SDA bus line for the proper amount of setup time (see Figure 5) before the next rising edge of SCL during a bit read. The device ...
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... The DS4550 is capable of writing bytes (1 page 2 or row) with a single I C write transaction. This is inter- ...
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I See Figure 6 for a read example using the repeated start condition to specify the starting memory location. Reading Multiple Bytes from a Slave: The read oper- ation can be used to read multiple bytes with a single transfer. ...
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... Chip Topology TRANSISTOR COUNT: 21,161 SUBSTRATE CONNECTED TO GROUND Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © ...