MAX6946 Maxim, MAX6946 Datasheet - Page 17

• Manufacturer Part Number: MAX6946
• Description: The MAX6946/MAX6947 I²C-/SMBus™-compatible, serial-interfaced peripherals provide microprocessors with 10 I/O ports rated to 7V
• Manufacturer: Maxim

Table 10. MAX6946/MAX6947 Slave
Addresses
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master fin-
ishes communicating with the slave, it issues a STOP
(P) condition by transitioning SDA from low to high
while SCL is high. The bus is then free for another
transmission (Figure 9).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 10).
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register
of the MAX6946/MAX6947 selected by the command
byte (Figure 11). If multiple data bytes are transmitted
before a STOP condition is detected, these bytes are
generally stored in subsequent MAX6946/MAX6947
internal registers because the command byte autoin-
crements (Table 1).
Read from the MAX6946/MAX6947 using the
MAX6946/MAX6947s’ internally stored command byte
as an address pointer the same way the stored com-
mand byte is used as an address pointer for a write.
The pointer autoincrements after each data byte is read
using the same rules as for a write (Table 1). Thus, a
read is initiated by first configuring the MAX6946/
MAX6947s’ command byte by performing a write
(Figures 12 and 13). The master can now read n con-
AD0 = GND
AD0 = V
MAX6947
MAX6946
DD
10-Port, Constant-Current LED Driver and
I/O Expander with PWM Intensity Control
______________________________________________________________________________________
Message Format for Reading
Start and Stop Conditions
SLAVE ADDRESS
010 0000
010 0100
010 0000
Acknowledge
Bit Transfer
secutive bytes from the MAX6946/MAX6947 with the
first data byte being read from the register addressed
by the initialized command byte (Figure 14). When per-
forming read-after-write verification, remember to reset
the command byte’s address because the stored com-
mand byte address has been autoincremented after
the write (Table 1).
Figure 9. Start and Stop Conditions
Figure 10. Bit Transfer
Figure 11. Acknowledge
TRANSMITTER
SDA
SCL
SDA
SCL
RECEIVER
CONDITION
SDA BY
SDA BY
START
SCL
S
CONDITION
START
DATA LINE STABLE;
S
DATA VALID
1
CHANGE OF DATA
ALLOWED
2
FOR ACKNOWLEDGE
CLOCK PULSE
8
CONDITION
9
STOP
P
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