MAX7315 Maxim, MAX7315 Datasheet - Page 15

• Manufacturer Part Number: MAX7315
• Description: The MAX7315 I²C-/SMBus™-compatible serial interfaced peripheral provides microprocessors with 8 I/O ports
• Manufacturer: Maxim

output port registers, and using the software or hard-
ware controls to flip between the patterns.
If the blink phase 1 register is written with 0xFF, then
the BLINK input can be used as a hardware disable to,
for example, instantly turn off an LED pattern pro-
grammed into the blink phase 0 register. This technique
can be further extended by driving the BLINK input with
a PWM signal to modulate the LED current to provide
fading effects.
The blink mode is enabled by setting the blink enable
flag E in the configuration register (Table 4). When blink
mode is enabled, the state of the blink flip flag sets the
phase, and the output ports are set by either the blink
Table 4. Configuration register (continued)
X = Don’t care.
output is controlled by the O0 and O1 bits
INT/O8 output is high impedance (blink is
output is low when interrupt enable (I bit)
Control, Interrupt, and Hot-Insertion Protection
INT/O8 output is high impedance during
INT/O8 output is high impedance during
INT/O8 outp ut i s low dur ing blink p hase 0
INT/O8 outp ut i s low dur ing blink p hase 1
Read-back data change interrupt status
Read-back data change interrupt status
—data change is detected, and INT/O8
Disable data change interrupt—INT/O8
Enable data change interrupt—INT/O8
INT/O8 output is low (blink is disabled)
output is controlled by port input data
INT/O8 output is high when interrupt
—data change is not detected, and
CONFIGURATION
enable (I bit) is set
blink phase 0
blink phase 1
REGISTER
disabled)
change
is set
______________________________________________________________________________________
8-Port I/O Expander with LED Intensity
R/W
—
—
—
—
—
—
—
—
1
1
ADDRESS
CODE
(HEX)
0x0F
INT
D7
X
X
X
X
X
X
X
0
1
phase 0 register or the blink phase 1 register (Table 7).
The blink mode is disabled by clearing the blink enable
flag E in the configuration register (Table 4). When blink
mode is disabled, the blink phase 0 register alone con-
trols the output ports.
When the blink function is disabled, the blink phase 0
register sets the logic levels of the 8 ports (P0 through
P7) when configured as outputs (Table 8). A duplicate
register called the blink phase 1 register is also used if
the blink function is enabled (Table 9). A logic high sets
the appropriate output port high impedance, while a
logic low makes the port go low.
D6
O
X
X
X
X
X
X
X
X
0
0
O1
D5
X
X
X
X
X
X
X
0
1
REGISTER DATA
D4
O0
X
X
X
X
X
0
1
0
1
Blink Phase Registers
D3
X
X
1
0
0
0
0
0
0
I
D2
G
X
X
X
X
X
X
X
X
X
D1
B
X
X
X
X
X
X
X
X
X
D0
E
X
0
0
1
1
1
1
X
X
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