STHDLS101AQTR STMicroelectronics, STHDLS101AQTR Datasheet - Page 9

• Manufacturer Part Number: STHDLS101AQTR
• Description: IC VIDEO LEVEL SHIFTER 48-QFN
• Manufacturer: STMicroelectronics
• Type: Level Shifterr

Specifications of STHDLS101AQTR

• Function: *
• Circuit: *
• On-state Resistance: *
• Voltage Supply Source: *
• Voltage - Supply, Single/dual (±): *
• Current - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Applications: Graphic Cards, VGA Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-9078-2

STHDLS101A
Table 2.
number
Pin
25
26
27
28
29
30
31
32
33
34
35
36
37
FUNCTION3
FUNCTION4
HPD_SINK
SDA_SINK
SCL_SINK
Pin description (continued)
DDC_EN
VCC33
VCC33
Name
OE_N
GND
GND
GND
GND
Vendor-specific
control or test
Output
Power
Power
Power
Power
Power
Power
Doc ID 15756 Rev 1
Type
Input
Input
Input
Input
pins
I/O
Enable for level shifter path. 3.3 V tolerant low-voltage
single-ended input. Internal pull-down enables chip
when unconnected
1
0
3.3 V±10% DC supply
Ground
5 V DDC Clock I/O. Pulled-up by external termination
to 5 V. Connected to SCL_SOURCE through voltage-
limiting integrated NMOS pass-gate
5V DDC Data I/O. Pulled-up by external termination to
5V. Connected to SDA_SOURCE through voltage-
limiting integrated NMOS pass-gate
Low-frequency, 0V to 5V (nominal) input signal. This
signal comes from the HDMI connector. Voltage high
indicates “plugged” state; voltage low indicates
“unplugged” state. HPD_SINK is pulled down by an
integrated 160KΩ pull-down resistor
Ground
Enables bias voltage to the DDC pass-gate level shifter
gates. (May be implemented as a bias voltage
connection to the DDC pass-gate themselves)
0 V
3.3 V
3.3 V±10% DC supply
Used for polarity control of the HPD_SOURCE output.
When L, the HPD_SOURCE is an open-drain output
sand when H, the HPD_SOURCE is a buffered output
(O V to V
Function pins are to enable vendor-specific features or
test modes
For normal operation, these pins are tied to GND or
VCC33
For consistent interoperability, GND is the preferred
default connection for these signals
Ground
Ground
DDC_EN
OE_N
CC
)
High-Z
50 Ω
Disabled
Enabled
termination
Function
IN_D
Pass-gate
Pin configuration
High-Z
Active
OUT_D Outputs
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