LMH1980MM/NOPB National Semiconductor, LMH1980MM/NOPB Datasheet - Page 10

• Manufacturer Part Number: LMH1980MM/NOPB
• Description: IC SEPARATOR VID SD/HD/PC 10MSOP
• Manufacturer: National Semiconductor
• Type: Video Syncr

Specifications of LMH1980MM/NOPB

• Applications: Displays, Projectors, Receivers
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH1980MMTR

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If a PC video input with bi-level sync is to be used, C
be removed to disable chroma filtering. This is necessary be-
cause HD will output logic high (like in the SD video input
case) and enable the filter. A chroma filter could severely
band-limit a high-bandwidth PC video signal, which could roll-
off and attenuate the sync pulses such that the LMH1980
cannot detect a valid input signal.
If some high-frequency noise filtering is needed for all video
inputs, a small capacitor (C
allel but outside of the transistor switch. When Q1 is turned
on, then C
Input Coupling Capacitor
The input signal should be AC coupled to the V
LMH1980 with a properly chosen coupling capacitor, C
The primary consideration in choosing C
LMH1980 will interface with video sources using an AC-cou-
pled output stage. If AC-coupled video sources are expected
in the end-application , then it’s recommended to choose a
small C
pulses due to average picture level changes. It’s important to
note that video sources with an AC-coupled output will cause
video-dependent jitter at the HSync output of the sync sepa-
rator. When only DC-coupled video sources are expected, a
larger value for C
sync output pulses. A smaller C
crease rejection of source AC hum components and also
reduce start-up time regardless of the video source's output
coupling type.
START-UP TIME
When there is a significant change to the video input signal,
such as sudden signal switching in, signal attenuation (i.e.:
load termination added via loop through) or signal gain (i.e.:
load termination removed), the quiescent operation of the
LMH1980 will be disrupted. During this dynamic input condi-
tion, the LMH1980 outputs may not be correct but will recover
to valid signals after a predictable start-up time, which con-
sists of an adjustable input settling time and a predetermined
“sync lock time”.
Input Settling Time and Coupling Capacitor Selection
Following a significant input condition, the negative sync tip
of the AC-coupled signal settles to the input clamp voltage as
the coupling capacitor, C
via the dynamic clamp current through V
termines the input settling time, its capacitance value is critical
when minimizing overall start-up time. A smaller C
yields shorter settling time at the expense of increased line
droop voltage, whereas a larger one yields reduced line droop
but longer settling time. Settling time is proportional to the
value of C
FIGURE 11. External Switch-Controlled Chroma Filter
IN
value such as 0.01 µF to avoid missing sync output
IN
1
, so doubling C
and C
IN
2
will be connected in parallel (C
may be used without concern for missing
IN
IN
, recovers a quiescent DC voltage
1
) may be optionally used in par-
will also double the settling time.
IN
value can be used to in-
IN
. Because C
IN
is whether the
IN
(pin 4) of the
1
+C
2
IN
should
2
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IN
IN
value
)
.
de-
10
Sync Lock Time
In addition to settling time, the LMH1980 has a predetermined
sync lock time, T
Once the AC-coupled input has settled enough, the LMH1980
needs time to detect the valid video signal and apply fixed-
level sync slicing before the output signals are correct.
For practical values of C
or 2 video fields in duration starting from the 1st valid VSync
output pulse to the valid HSync pulses beginning thereafter.
VSync and HSync pulses are considered valid when they
align correctly with the input's vertical and horizontal sync in-
tervals.
It is recommended for the outputs to be applied to the system
after the start-up time is satisfied and outputs are valid. For
example, the oscilloscope screenshot in Figure 12 shows a
typical start-up time within 1 video field from when an NTSC
signal is just applied to when the LMH1980 outputs are valid.
LOGIC OUTPUTS
In the absence of a video input signal, the LMH1980 outputs
are logic high except for the odd/even field, which is undefined
and depends on its previous state, and the composite sync
output.
Horizontal Sync Output
HSOUT (pin 6) produces a negative-polarity horizontal sync
signal, or HSync, extracted from the input signal. For bi-level
and tri-level sync signals, HSync's negative-going leading
edge is derived from the input's sync reference, O
propagation delay.
Important: The HSync output has good performance on its
negative-going leading edge, so it should be used as the ref-
erence to a negative-edge triggered PLL input. If HSync is
used as the reference to a positive-edge triggered PLL input,
like in some FPGAs, the signal must be inverted first to pro-
duce a positive-polarity HSync signal (i.e.: positive-going
leading edge) before the PLL input. HSync's trailing edge
should not be used as the reference to a PLL because for a
NTSC/PAL input, the input's half-width pulses (½T
vertical interval cause the trailing edges of the HSync output
to occur earlier than for the normal-width sync pulses
(T
edge, as shown in Figure 13, could affect the performance of
the PLL. The bi-modal trailing edge timing also occurs on the
CSync output as well.
SYNC
FIGURE 12. Typical Start-Up Time for NTSC Input to
). This bi-modal timing variation on HSync's trailing
SYNC-LOCK
LMH1980 (C
IN
, T
, before the outputs are correct.
SYNC-LOCK
IN
= 0.1 µF)
is typically less than 1
SYNC
H
, with a
) in the
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