ADV7162KS140 Analog Devices Inc, ADV7162KS140 Datasheet

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FEATURES 96-Bit Pixel Port for 1600 1280 220 MHz, 24-Bit (30-Bit Gamma Corrected) True-Color Triple 10-Bit “Gamma Correcting” D/A Converters 2% (max) DAC to DAC Color Matching Triple 256 10 (256 x 30) Color Palette RAM On-Board User Definable ...

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ADV7160/ADV7162–SPECIFICATIONS Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity Gray Scale Error Coding DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance CLOCK INPUTS ...

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TIMING CHARACTERISTICS CLOCK CONTROL AND PIXEL PORT Parameter 220 MHz Version f 220 CLOCK LOADIN 2:1 Multiplexing 110 4:1 Multiplexing 55 8:1 Multiplexing 27 ...

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ADV7160/ADV7162 8,9 MPU P ORT Parameter 220 MHz 170 MHz Version Version ...

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TIMING CHARACTERISTICS (Cont.) JTAG P ORT Parameter 4 PLL PERFORMANCE Jitter PLL REFERENCE INPUT PLL Frequency REF PLL Period REF PLL Duty Cycle REF JTAG PERFORMANCE TCK Frequency TCK High Time TCK ...

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ADV7160/ADV7162 Timing Waveforms CLOCK CLOCK t 4 LOADOUT (2:1 MULTIPLEXING) LOADOUT (4:1 MULTIPLEXING) LOADOUT (8:1 MULTIPLEXING) Figure 3. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK ) LOADIN PIXEL INPUT VALID DATA DATA ...

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CLOCK LOADOUT LOADIN PIXEL A ... A ... N N+1 INPUT N+1 DATA ANALOG OUTPUT DATA (IOR, IOG, IOB, A ... H SYNCOUT) N–1 N– Figure 5. Pixel Input to Analog Output Pipeline with Minimum ...

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ADV7160/ADV7162 CLOCK LOADOUT LOADIN PIXEL A ... A ... N INPUT N DATA N+1 ANALOG OUTPUT DATA (IOR, IOG, IOB, SYNCOUT Figure 7. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay ...

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CLOCK LOADOUT LOADIN PIXEL A ... A ... N N+1 INPUT N+1 DATA ANALOG OUTPUT DATA (IOR, IOG, IOB, SYNCOUT) Figure 9. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (2:1 Multiplex Mode) ...

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ADV7160/ADV7162 CLOCK PRGCKOUT (CLOCK/4) PRGCKOUT (CLOCK/8) PRGCKOUT (CLOCK/16) PRGCKOUT (CLOCK/32 Figure 11. Pixel Clock Input vs. Programmable Clock Output (PRGCKOUT SCKIN BLANK SCKOUT Figure 12. Video Data Shift Clock Input (SCKIN) & BLANK vs. Video Data ...

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... ESD precautions are recommended to avoid performance degradation or loss of functionality. REV R R 120 + 0 121 PIN NO. 1 IDENTIFIER 160 140 MHz 3 ADV7160KS140 1 4 ADV7162KS140 –11– ADV7160/ADV7162 160-Lead QFP Configuration 81 ROW C ADV7160/ADV7162 QFP TOP VIEW (NOT TO SCALE) ROW A 40 WARNING! ESD SENSITIVE DEVICE 80 41 ...

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ADV7160/ADV7162 Pin No. Mnemonic Pin No ...

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Mnemonic Function RED ( – GREEN ( Pixel Port (TTL Compatible Inputs): 96 pixel select inputs, with 8 bits each for Red, Green and Blue. Each ...

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ADV7160/ADV7162 Mnemonic Function SYNCOUT Composite-Sync Output (TTL Compatible Output). This video output is a delayed version of SYNC. The delay corresponds to the number of pipeline stages of the device. TRISYNC Composite-Sync HDTV Control (TTL Compatible Output). This video input ...

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The ADV7160/ADV7162 integrates a number of graphic func- tions onto one device allowing 24-bit direct True-Color (30-bit Corrected-Color) operation at the maximum screen resolution of 1600 1280 at a refresh rate of 85 Hz. The ADV7160/ ...

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ADV7160/ADV7162 Other pixel data signals latched into the device by LOADIN include SYNC, BLANK, TRISYNC and PS0 Internally, data is pipelined through the part by the differential pixel clock inputs, CLOCK and CLOCK or by the internal pixel clock generated ...

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PLL PLL REF CLOCK ECL TO TTL CLOCK DIVIDE BY PRGCKOUT LOADOUT SCKOUT LATCH TRISYNC BLANK EN SYNC SCKIN ADV7160/ ADV7162 LOADIN TO COLOR DATA MULTIPLEXER FUNCTION OF ...

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ADV7160/ADV7162 The SCKOUT signal is essentially the video memory shift con- trol signal stopped during the screen retrace. Figure 19 shows a suggested frame buffer to ADV7160/ADV7162 interface. This is a minimum chip solution and allows the ADV7160/ADV7162 ...

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COLOR VIDEO MODES The ADV7160/ADV7162 supports a number of color video modes all at the maximum video rate. Command bits CR27–CR24 of Command Register 2 along with bit MR11 of Mode Register 1 determine the color mode. Seven color modes ...

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ADV7160/ADV7162 256 x 10 RAM LOCATION "0" ...

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...

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ADV7160/ADV7162 The unused Blue pixel inputs are used, in this mode, to provide 8 extra PS inputs. These PS inputs provide 2 bits after 8:1 mul- tiplexing. The PS inputs can be used as Overlay or Palette Se- lect inputs. ...

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ADDRESS CONTROL REGISTER REGISTERS (A10–A0) CURSOR IMAGE 7FFH – 400H RESERVED 3FFH – 305H CURSOR COLOR 1 304H CURSOR COLOR 2 303H RESERVED 302H – 205H CURSOR CONTROL REG 204H CURSOR Y-HI REG 203H CURSOR Y-LO ...

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ADV7160/ADV7162 Power-On Reset On power-up, the ADV7160/ADV7162 executes a power-on re- set operation. This initializes the pixel port such that the pixel sequence ABCD starts at A. The Mode Register (MR17–MR10), Command Register 2 (CR27–CR20), Command Register 3 (CR37–CR30) have ...

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Register Accesses The MPU can write to or read from all of the ADV7160/ ADV7162’s registers. C0 and C1 determine whether the Mode Register or Address Register is being accessed. Access to these Write Operation Palette ...

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ADV7160/ADV7162 REGISTER PROGRAMMING The following section describes each register, including Address Register, Mode Register and each of the Control Registers in terms of its configuration. Address Register (A10–A0) As illustrated in the previous tables, the C1 and C0 control in- ...

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MPU access to the Control Register. When accessing Control Registers in the range 200H to 204H, and when accessing the cursor image, the Address Register auto- increments after each register access. On accessing the last cur- sor ...

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ADV7160/ADV7162 CR29 CR28 CR27 RESERVED* TRUE COLOR/PSEUDO COLOR MODE CONTROL CR27 CR26 CR25 CR24 8-BIT PSEUDO COLOR ON R7– 8-BIT PSEUDO COLOR ON G7– 8-BIT PSEUDO COLOR ON ...

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CR39 CR38 RESERVED* * THESE BITS ARE READ-ONLY RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "00." Pixel Multiplex Control CR37 CR36 0 0 1:1 MUXING: LOADOUT = CLOCK 0 1 2:1 MUXING: LOADOUT = CLOCK 1 0 8:1 MUXING: ...

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ADV7160/ADV7162 Signature Reset Control (CR46) Taking CR46 low then high resets the signature analyzer. This is done to give a known starting point before acquiring a signature. Signature Acquire Control (CR47) This bit should be set to Logic “1” for ...

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PLL V Register (Address Reg (A10–A0) = 00FH) This register is a read only 10-bit register. However V9–V8 are reserved bits, containing zeros. Bit read only bit. This bit should be masked in software on readback as ...

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ADV7160/ADV7162 CCR9 CCR8 CCR7 RESERVED* * THESE BITS ARE READ-ONLY RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "00." Figure 45. Cursor Control Register (CCR) (CCR9–CCR0) DIGITAL-TO-ANALOG CONVERTER (DACS) AND VIDEO OUTPUTS The ADV7160/ADV7162 contains three high speed video DACs. ...

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O/P with Sync Description Enabled (mA) WHITE LEVEL 26.67 VIDEO Video + 9.05 VIDEO to BLANK Video + 1.44 BLACK LEVEL 9.05 BLACK to BLANK 1.44 BLANK LEVEL 7.62 SYNC LEVEL 0 Variations on RS-343A Various other video output configurations ...

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ADV7160/ADV7162 BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7160/ADV7162 is a highly integrated circuit contain- ing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the ...

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0.1µF COMP V REF R SET ADV7160 IOR IOG IOB GND NOTES: 1. ALL RESISTERS ARE 1% METAL FILM 2. 0.1µF AND 0.01µF CAPACITORS ARE CERAMIC 3. ADDITIONAL DIGITAL CIRCUITRY OMITTED FOR CLARITY REV. ...

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ADV7160/ADV7162 CLOCK GRAPHICS PROCESSOR/ CONTROLLER BLANK SYNC / TRISYNC FRAME BUFFER/ VIDEO MEMORY VRAM 50 MHZ (BANK A) VRAM 50 MHZ (BANK B) VRAM 50 MHZ (BANK C) VRAM 50 MHZ (BANK D) APPENDIX 2 TYPICAL FRAME BUFFER INTERFACE PLL ...

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DACs 10-Bit RAM-DAC resolution allows for nonlinear video correc- tion, in particular Gamma Correction. The ADV7160/ADV7162 allows for an increase in color resolution from 24-bit to 30-bit effective color without the necessity of a 30-bit deep frame buffer. In ...

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ADV7160/ADV7162 ADV7160/ADV7162 INITIALIZATION After power has been supplied, the ADV7160/ADV7162 must be initialized. The Mode Register and Control Registers must then be set up. The values written to the various registers will be determined by the desired operating mode of ...

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Example Color Mode: 24-Bit Gamma Corrected True Color (30-Bits) through Color Palette Multiplexing: 2:1, Databus: 10-Bit, RAM-DAC Resolution: 10-Bit, SYNC: on Green, Pedestal: 0 IRE, Calibration: Every Vertical Sync, Internal PLL: 220 MHz (Reference = 15 MHz) Register Initialization Write ...

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ADV7160/ADV7162 SIGNATURE REGISTER I/P S19 '0' '0' Signature Register The ...

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TDI CE R THREE-STATE CONTROL LOADIN SCKIN SCKOUT CLOCK CLOCK LOADOUT PRGCKOUT PS0 A PS0 B PS0 C PS0 D PS1 A PS1 B PS1 C PS1 D ...

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ADV7160/ADV7162 THERMAL AND ENVIRONMENTAL CONSIDERATIONS The ADV7160/ADV7162 is a very highly integrated monolithic silicon device. This high level of integration, in such a small package, inevitably leads to consideration of thermal and envi- ronmental conditions which the ADV7160/ADV7162 must op- ...

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PAGE INDEX Topic FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ADV7160/ADV7162 0.037 (0.95) 0.026 (0.65) SEATING PLANE 0.004 (0.10) MAX 0.070 (1.77) 0.062 (1.57) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). S-160 160-Lead Plastic Quad Flatpack 1.239 (31.45) SQ 1.219 (30.95) 0.160 (4.07) MAX 1.107 (28.10) SQ 1.100 (27.90) ...