AD8324JRQ Analog Devices Inc, AD8324JRQ Datasheet - Page 4

• Manufacturer Part Number: AD8324JRQ
• Description: IC LINE DRIVER CBL 3.3V 20-QSOP
• Manufacturer: Analog Devices Inc
• Type: Line Driver, Transmitterr

Specifications of AD8324JRQ

• Rohs Status: RoHS non-compliant
• Applications: Modems, CATV
• Mounting Type: Surface Mount
• Package / Case: 20-QSOP

AD8324
LOGIC INPUTS (TTL/CMOS COMPATIBLE LOGIC)
DATEN , CLK, SDATA, TXEN, SLEEP , V
Table 2.
Parameter
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current (V
Logic 0 Current (V
Logic 1 Current (V
Logic 0 Current (V
Logic 1 Current (V
Logic 0 Current (V
TIMING REQUIREMENTS
V
Table 3.
Parameter
Clock Pulse Width (t
Clock Period (t
Setup Time SDATA vs. Clock (t
Setup Time DATEN vs. Clock (t
Hold Time SDATA vs. Clock (t
Hold Time DATEN vs. Clock (t
Input Rise and Fall Times, SDATA, DATEN , Clock (t
ANALOG
OUTPUT
SDATA
DATEN
CC
TXEN
CLK
= 3.3 V, t
t
DS
SIGNAL AMPLITUDE (p-p)
t
ES
R
t
VALID DATA WORD G1
VUH
C
8 CLOCK CYCLES
= t
)
MSB . . . LSB
INH
INL
INH
INL
INH
INL
F
Figure 3. Serial Interface Timing
= 4 ns, f
WH
t
= 0 V), CLK, SDATA, DATEN
= 0 V), TXEN
= 0 V), SLEEP
C
= 3.3 V), CLK, SDATA, DATEN
= 3.3 V), TXEN
= 3.3 V), SLEEP
)
t
EH
CLK
GAIN TRANSFER (G1)
DH
EH
t
GS
DS
ES
)
)
= 8 MHz, unless otherwise noted.
)
)
t
OFF
VALID DATA WORD G2
CC
= 3.3 V, unless otherwise noted.
R
, t
t
F
CN
)
GAIN TRANSFER (G2)
Rev. A | Page 4 of 16
SDATA
CLK
MSB
Min
16.0
32.0
5.0
15.0
5.0
3.0
Min
2.1
0
0
−600
50
−250
50
−250
t
DS
Figure 4. SDATA Timng
VALID DATA BIT
MSB-1
Typ
Typ
t
DH
Max
10
Max
3.3
0.8
20
−100
190
−30
190
−30
MSB-2
Unit
ns
ns
ns
ns
ns
ns
ns
Unit
V
V
nA
nA
μA
μA
μA
μA