MAX9126 Maxim, MAX9126 Datasheet

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MAX9126

Manufacturer Part Number
MAX9126
Description
The MAX9125/MAX9126 quad low-voltage differential signaling (LVDS) line receivers are ideal for applications requiring high data rates, low power, and reduced noise
Manufacturer
Maxim
Datasheet
The MAX9125/MAX9126 quad low-voltage differential
signaling (LVDS) line receivers are ideal for applica-
tions requiring high data rates, low power, and reduced
noise. The MAX9125/MAX9126 are guaranteed to
receive data at speeds up to 500Mbps (250MHz) over
controlled-impedance media of approximately 100Ω.
The transmission media may be printed circuit (PC)
board traces or cables.
The MAX9125/MAX9126 accept four LVDS differential
inputs and translate them to 3.3V CMOS outputs. The
MAX9126 features integrated parallel termination resis-
tors (nominally 115Ω), which eliminate the requirement
for four discrete termination resistors and reduce stub
length. The MAX9125 inputs are high impedance and
require an external termination resistor when used in a
point-to-point connection.
The devices support a wide common-mode input range
of 0.05V to 2.35V, allowing for ground potential differ-
ences and common-mode noise between the driver
and the receiver. A fail-safe feature sets the output high
when the inputs are open, or when the inputs are
undriven and shorted or parallel terminated. The EN
and EN inputs control the high-impedance output and
are common to all four receivers. Inputs conform to the
ANSI TIA/EIA-644 LVDS standard. The MAX9125/
MAX9126 operate from a single +3.3V supply, are
specified for operation from -40°C to +85°C, and are
available in 16-pin TSSOP and SO packages. Refer to
the MAX9124 data sheet for a quad LVDS line driver.
19-1908; Rev 0; 5/01
Pin Configuration appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Digital Copiers
Laser Printers
Cellular Phone Base Stations
Add/Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches/Routers
Backplane Interconnect
Clock Distribution
________________________________________________________________ Maxim Integrated Products
General Description
Applications
Quad LVDS Line Receivers with
Integrated Termination
o Integrated Termination Eliminates Four External
o Pin Compatible with DS90LV032A
o Guaranteed 500Mbps Data Rate
o 300ps Pulse Skew (max)
o Conform to ANSI TIA/EIA-644 LVDS Standard
o Single +3.3V Supply
o Low 70µA Shutdown Supply Current
o Fail-Safe Circuit
LVTTL/LVCMOS
Resistors (MAX9126)
DATA INPUT
MAX9125EUE
MAX9126EUE
MAX9125ESE
MAX9126ESE
PART
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
MAX9124
Typical Application Circuit
T
T
T
T
X
X
X
X
LVDS SIGNALS
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Ordering Information
115Ω
115Ω
115Ω
115Ω
MAX9126
R
R
R
R
PIN-PACKAGE
16 TSSOP
16 SO
16 TSSOP
16 SO
X
X
X
X
Features
LVTTL/LVCMOS
DATA OUTPUT
1

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MAX9126 Summary of contents

Page 1

... EN inputs control the high-impedance output and are common to all four receivers. Inputs conform to the ANSI TIA/EIA-644 LVDS standard. The MAX9125/ MAX9126 operate from a single +3.3V supply, are specified for operation from -40°C to +85°C, and are available in 16-pin TSSOP and SO packages. Refer to the MAX9124 data sheet for a quad LVDS line driver ...

Page 2

... +3. Figure 1 DIFF CC Open, undriven short undriven 100Ω parallel -4.0mA termination (MAX9125 +100mV Open or undriven short OH -4.0mA V = +100mV (MAX9126 +4.0mA -100mV Enabled +100mV (Note OUT I Disabled OUT ...

Page 3

... Differential Part-to-Part Skew (Note 8) Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency (Note 9) _______________________________________________________________________________________ Quad LVDS Line Receivers with Integrated Termination | | V = 0.1V to 1.0V, common-mode voltage ...

Page 4

... V , and Note 2: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification. Note 3: AC parameters are guaranteed by design and characterization. Note 4: C includes scope probe and test jig capacitance. L Note the magnitude difference of differential propagation delays in a channel; t ...

Page 5

V = 200mV +1.2V DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE 2.6 2.5 t PHLD 2.4 2.3 t PLHD 2.2 0 0.5 1.0 1.5 2.0 COMMON-MODE VOLTAGE (V) PULSE SKEW ...

Page 6

... The LVDS standards specify an input voltage range 2.4V referenced to receiver ground. The MAX9126 has an integrated termination resistor internally connected across each receiver input. The internal termination saves board space, eases layout, and reduces “stub length” compared to an external ter- mination resistor ...

Page 7

... Figure 4. High-Z Delay Test Circuit _______________________________________________________________________________________ Quad LVDS Line Receivers with Integrated Termination IN_+ PULSE** GENERATOR IN_- 50Ω* 50Ω* *50Ω REQUIRED FOR PULSE GENERATOR. **WHEN TESTING MAX9126, ADJUST THE PULSE GENERATOR OUTPUT TO ACCOUNT FOR INTERNAL TERMINATION RESISTOR (DIFFERENTIAL PLHD 80% 50% 20% t ...

Page 8

... PHZ OUTPUT WHEN V = +100mV ID Figure 5. High-Z Delay Waveforms The fail-safe feature of the MAX9125/MAX9126 sets the output high when: • Inputs are open. • Inputs are undriven and shorted. • Inputs are undriven and terminated. A fail-safe circuit is important because under these conditions, noise at the inputs may switch the receiver and it may appear to the system that data is being received ...

Page 9

... EMI due to canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. The MAX9126 has an integrated termination resistor connected across the inputs of each receiver. The value of the integrated resistor is specified in the DC characteristics. ...

Page 10

... GND 8 TSSOP/SO 10 ______________________________________________________________________________________ N1+ Rx OUT1 R DIFF N2+ Rx OUT2 R DIFF N3+ Rx OUT3 R DIFF N4+ Rx OUT4 R DIFF I N4 MAX9125 GND IN4- 14 IN4+ 13 OUT4 OUT3 10 IN3+ 9 IN3- Functional Diagram OUT1 Rx OUT2 Rx OUT3 OUT4 Rx MAX9126 GND ...

Page 11

Quad LVDS Line Receivers with ______________________________________________________________________________________ Integrated Termination Package Information 11 ...

Page 12

... Integrated Termination Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product ...

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