MAX9157 Maxim, MAX9157 Datasheet - Page 10

• Manufacturer Part Number: MAX9157
• Description: The MAX9157 is a quad bus LVDS (BLVDS) transceiver for heavily loaded, half-duplex multipoint buses
• Manufacturer: Maxim

matching the differential impedance of the bus (taking
into account any reduced impedance due to loading).
The characteristics of input and output connections
affect the performance of the MAX9157. Use con-
trolled-impedance traces, cables, and connectors with
matched characteristic impedance.
Ensure that noise couples as common mode by run-
ning the traces of a differential pair close together.
Reduce within-pair skew by matching the electrical
length of the traces of a differential pair. Excessive
skew can result in a degradation of magnetic field can-
cellation. Maintain the distance between traces of a dif-
ferential pair to avoid discontinuities in differential
impedance. Minimize the number of vias to further pre-
vent impedance discontinuities.
Quad Bus LVDS Transceiver
Table 3. Receiver Mode
Table 4. Input Internal Pullup/Pulldown
Resistors
10
RE_
L
L
L
H
DE12
DE34
RE12
RE34
DIN_
______________________________________________________________________________________
PIN
Fail-safe operation guaranteed when
DO_+/RIN_+ and DO_-/RIN_- are
open, undriven and shorted, or
undriven and parallel terminated
V
ID
= (V
Traces, Cables, and Connectors
DO_+
INPUTS
V
V
ID
ID
/R
< -100mV
> 100mV
IN_+
INTERNAL RESISTOR
X
) - (V
Pulldown to GND
Pulldown to GND
Pullup to V
Pullup to V
Pullup to V
DO_-
/R
IN_-
CC
CC
CC
)
OUTPUTS
RO_
H
H
L
Z
Avoid the use of unbalanced cables, such as ribbon
cable. Balanced cables, such as twisted pair, offer
superior signal quality and tend to generate less EMI
due to canceling effects. Balanced cables tend to pick
up noise as common mode, which is rejected by the
receiver.
A four-layer PC board that provides separate power,
ground, input, and output signals is recommended.
Keep the LVTTL/LVCMOS and BLVDS signals separat-
ed to prevent coupling.
Figure 2. Driver V
Figure 3. Driver Propagation Delay and Transition Time Test Circuit
GND
GENERATOR
V
CC
DIN_
OD
50Ω
and V
DIN_
OS
R
R
Test Circuit
L
L
/2
/2
D0_+/RIN_+
DO_-/RIN_-
V
C
C
OS
L
L
Board Layout
V
OD
R
L
DO_+/RIN_+
DO_-/RIN_-