MAX9213 Maxim, MAX9213 Datasheet
MAX9213
Available stocks
Related parts for MAX9213
MAX9213 Summary of contents
Page 1
... Rev 4; 10/07 General Description The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9213 feature programmable DC bal- ance, which allows isolation between the serializer and deserializer using AC-coupling. The DC balance circuits on each channel code the data, limiting the imbalance of transmitted ones and zeros to a defined range ...
Page 2
... Storage Temperature Range .............................-65°C to +150°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
Page 3
... MAX9213 66MHz MAX9213 10MHz MAX9209 I 20MHz MAX9209 CCW 33MHz MAX9209 40MHz MAX9209 Non-DC-balanced mode, worst-case 20MHz MAX9213 pattern 5pF, L Figure 2 33MHz MAX9213 40MHz MAX9213 66MHz MAX9213 85MHz MAX9213 PWRDWN = low I CCZ 21-Bit Serializers MIN TYP MAX -0.5 ±0.1 +0 ...
Page 4
... MAX9209 non-DC- balanced mode, 20MHz MAX9213 Figure 5 (Note 6) 40MHz MAX9213 85MHz MAX9213 8MHz MAX9209 16MHz MAX9209 34MHz MAX9209 DC-balanced mode, Figure 6 16MHz MAX9213 (Note 6) 34MHz MAX9213 66MHz MAX9213 MIN TYP MAX UNITS 150 280 400 ps 150 260 ...
Page 5
... Serializers MIN TYP MAX 0.3 x TCIP 0 0.3 x TCIP 0 2.2 0 3.5 4.5 6.0 4.7 5.9 7.2 32800 x TCIP 250 WORST-CASE AND PRBS SUPPLY CURRENT vs. FREQUENCY 120 MAX9213 NON-DC-BALANCED MODE 100 80 WORST-CASE PATTERN FREQUENCY (MHz) UNITS ...
Page 6
... EYE DIAGRAM—NON-DC-BALANCED MODE TxCLK IN = 85MHz DC-COUPLED 100mV/div 0V DIFFERENTIAL 7 ALL-CHANNELS PRBS PATTERN SWITCHING 100Ω TERMINATION 300ps/div MAX9213 EYE DIAGRAM—DC-BALANCED MODE TxCLK IN = 66MHz AC-COUPLED 2m OF CAT-5 UTP CABLE USING 0.1μF CAPACITORS 0V DIFFERENTIAL PRBS PATTERN ALL-CHANNELS 100Ω TERMINATION ...
Page 7
... Inverting Channel 1 LVDS Serial Data Output TxOUT0+ Noninverting Channel 0 LVDS Serial Data Output TxOUT0- Inverting Channel 0 LVDS Serial Data Output LVTTL/LVCMOS DC-Balance Programming Input: MAX9209: pulled DCB/NC MAX9213: pulled See Table 1. EP Exposed Paddle. Solder to ground. Pin Description FUNCTION CC CC ...
Page 8
Programmable DC-Balanced 21-Bit Serializers TxOUT_- OR TxCLK OUT- TxOUT_+ OR TxCLK OUT+ ΔVOS = |VOS(+) - VOS(-)| (TxOUT_+) - (TxOUT_-) OR (TxCLK OUT+) - (TxCLK OUT-) Figure 1. LVDS Output DC Parameters Figure 2. Worst-Case Test Pattern TxOUT_+ OR TxCLK ...
Page 9
... In DC-balanced mode, 9 bits are serialized every clock cycle (7 data bits + 2 DC-bal- ance bits). The highest data rate in DC-balanced mode for the MAX9213 is 66MHz 594Mbps. In non-DC- balanced mode, the maximum data rate is 85MHz 595Mbps. A bit time is 1 divided by the data rate, for example 595Mbps = 1 ...
Page 10
Programmable DC-Balanced 21-Bit Serializers TxCLK OUT (DIFFERENTIAL) CYCLE TxOUT2 DCA2 DCB2 (SINGLE ENDED) TxOUT1 DCA1 DCB1 (SINGLE ENDED) TxOUT0 DCA0 DCB0 (SINGLE ENDED) TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TPPos7 TPPos8 Figure 6. DC-Balanced Mode LVDS ...
Page 11
PWRDWN V CC TxCLK IN TxOUT_, TxCLK OUT HIGH-Z Figure 9. PLL Set Time PWRDWN TxCLK IN TxOUT_, TxCLK OUT Figure 10. Power-Down Delay TxCLK OUT+ TxCLK OUT- CYCLE DCA2 DCB2 TxIN20 TxIN19 TxIN18 TxOUT2 DCA1 DCB1 ...
Page 12
... TxOUT2 TxIN8 TxIN7 TxIN13 TxIN12 TxIN11 TxOUT1 TxIN1 TxIN6 TxIN5 TxIN0 TxOUT0 Figure 12. Non-DC-Balanced Mode Inputs Mapped to LVDS Outputs MAX9209 MAX9213 7 7:1 7 TxIN 7:1 7 7:1 PWRDWN PLL TxCLK IN 21:3 SERIALIZER Figure 13. DC-Coupled Link, Non-DC-Balanced Mode AC-Coupling Benefits Bit errors experienced with DC-coupling can be elimi- nated by increasing the receiver common-mode volt- age range by AC-coupling ...
Page 13
... All signal and control inputs except DCB/NC are 5V tol- erant and are internally pulled down to GND. The DCB/NC pin has a pullup on the MAX9209/MAX9213. DCB/NC Pin Default Conditions The MAX9209/MAX9213 have programmable DC bal- ance/non-DC balance. See Table 1 for DCB/NC default settings and operating modes ...
Page 14
... Programmable DC-Balanced 21-Bit Serializers MAX9209 MAX9213 2):1 7 TxIN (7 + 2): 2):1 PWRDWN PLL TxCLK IN 21:3 SERIALIZER Figure 15. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode Applications Information Selection of AC-Coupling Capacitors Voltage droop and the DSV of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter ...
Page 15
... DSV Integrated Termination The MAX9209/MAX9213 have an integrated output ter- mination resistor across each of the four LVDS outputs. These resistors damp reflections from induced noise and mismatches between the transmission line impedance and termination resistor at the deserializer input. In DC- balanced mode, the differential output resistance is part of the RC time constant ...
Page 16
... Programmable DC-Balanced 21-Bit Serializers The MAX9209/MAX9213 ESD tolerance is rated for IEC 61000-4-2, Human Body Model and ISO 10605 stan- dards. IEC 61000-4-2 and ISO 10605 specify ESD toler- ance for electronic systems. The IEC 61000-4-2 discharge components are C = 150pF and R S (Figure 16). For IEC 61000-4-2, the LVDS outputs are ...
Page 17
... CC TxIN13 15 TxIN14 16 GND 17 TxIN15 18 TxIN16 19 TxIN17 TxIN18 22 TxIN19 23 GND 24 TSSOP Chip Information MAX9209 TRANSISTOR COUNT: 9458 MAX9213 TRANSISTOR COUNT: 9458 PROCESS: CMOS ______________________________________________________________________________________ Programmable DC-Balanced 48 TxIN3 47 TxIN2 46 GND 45 TxIN1 44 TxIN0 43 DCB/NC 42 LVDS GND 41 TxOUT0- 40 TxOUT0+ TxIN8 1 39 TxOUT1- ...
Page 18
... Programmable DC-Balanced 21-Bit Serializers (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) N MARKING AAA TOP VIEW SIDE VIEW NOTES: 1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH. ...
Page 19
... For the latest package outline information go to www.maxim-ic.com/packages.) ______________________________________________________________________________________ Programmable DC-Balanced 21-Bit Serializers Package Information (continued) 19 ...
Page 20
... Programmable DC-Balanced 21-Bit Serializers (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 20 ______________________________________________________________________________________ Package Information (continued) ...
Page 21
... Removed all references to MAX9211 and MAX9215. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © ...