MAX9222 Maxim, MAX9222 Datasheet
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MAX9222
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MAX9222 Summary of contents
Page 1
... Programmable DC Balance or Non-DC Balance ♦ DC Balance Allows AC-Coupling for Wider Input Common-Mode Voltage Range ♦ As Low as 8MHz Operation (MAX9210/MAX9220) ♦ Falling-Edge Output Strobe (MAX9220/MAX9222) ♦ Slower Output Transitions for Reduced EMI (MAX9210/MAX9220) ♦ High-Impedance Outputs when PWRDWN is Low Allow Output Busing ♦ ...
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... -100µA OH RxCLK OUT MAX9210/ OH MAX9220 I = -2mA RxOUT_ OH MAX9214/MAX9222 I = 100µA OL RxCLK OUT MAX9210 MAX9220 I = 2mA OL RxOUT_ MAX9214/MAX9222 PWRDWN = low -0. 0.3V OUT_ CCO = 1.5kΩ 100pF 330Ω 150pF 2kΩ 330pF 0.05V to ID MIN TYP MAX 2 ...
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... MAX9220 DC- balanced mode CCO MAX9214/ = 3.0V to 3.6V, MAX9222 Figure 2 I MAX9210/ CCW MAX9220 C = 8pF, worst L case pattern, non-DC-balanced mode CCO = 3.0V to 3.6V, MAX9214/ Figure 2 MAX9222 PWRDWN = low I CCZ 21-Bit Deserializers MIN TYP MAX -10 -40 -5 -20 -10 -40 -28 -75 -14 -37 -28 -75 50 -50 -25 +25 -25 +25 ...
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... RxCLK OUT 0.9V , CCO Figure 3 MAX9214/MAX9222 RxOUT_ 0.9V MAX9210/ CCO to MAX9220 RxCLK OUT 0.1V , CCO Figure 3 MAX9214/MAX9222 8MHz 16MHz DC-balanced mode, Figure 4 (Note 6) 34MHz 66MHz 10MHz 20MHz Non-DC-balanced mode, Figure 4 (Note 6) 40MHz 85MHz Figures 5a, 5b Figures 5a, 5b Figures 5a, 5b Figures 5a, 5b Figures 6a, 6b ...
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PWRDWN = high, differential input voltage ⏐ +3.3V CCO +25°C, unless otherwise noted.) A WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs. FREQUENCY 100 MAX9220 DC-BALANCED MODE 90 80 WORST-CASE ...
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... LVTTL/LVCMOS DC-Balance Programming Input: MAX9210: pulled MAX9214: pulled MAX9220: pulled MAX9222: pulled See Table 1. LVDS Ground Inverting Channel 0 LVDS Serial Data Input Noninverting Channel 0 LVDS Serial Data Input Inverting Channel 1 LVDS Serial Data Input ...
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... In DC-balanced mode, 9 bits are deserialized every clock cycle (7 data bits + 2 DC- balance bits). The highest data rate in DC-balanced mode for the MAX9214 and MAX9222 is 66MHz 594Mbps. In non-DC-balanced mode, the maximum data rate is 85MHz 595Mbps. ...
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Programmable DC-Balance 21-Bit Deserializers RxOUT_ OR RxCLK OUT 8pF Figure 3. Output Load and Transition Times IDEAL SERIAL BIT TIME RSKM RSKM IDEAL MIN MAX INTERNAL STROBE Figure 4. LVDS Receiver Input Skew Margin RCIP RxCLK OUT 2.0V 2.0V 0.8V ...
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... Two complementary bits are appended to each group of 7 parallel input data bits to indicate to the MAX9210/ MAX9214/MAX9220/MAX9222 deserializers whether the data bits are inverted (see Figures 9 and 10). The deserializer restores the original state of the parallel data ...
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... The RC network for an AC-coupled link consists of the LVDS receiver termination resistor (R output resistor (R ), and the series AC-coupling capac- O itors (C). The RC time constant for two equal-value MAX9210 MAX9214 MAX9220 MAX9222 TRANSMISSION LINE TxOUT RxIN 100Ω 100Ω 100Ω 100Ω TxCLK OUT ...
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... transition time ( 100%). droop (% of signal amplitude). Jitter due to 2% droop and assumed 1ns transition time is: 21-Bit Deserializers MAX9210 MAX9214 MAX9220 MAX9222 RxIN 7 1:( 1:( RxOUT 7 1:( PWRDWN PLL RxCLK OUT 3:21 DESERIALIZER ) is the period of the parallel clock divided by ...
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... Equation 1 altered for four series capacitors (Figure 13) is DSV)/( The MAX9210/MAX9214/MAX9220/MAX9222 have fail- safe LVDS inputs in non-DC-balanced mode (Figure 1). Fail-safe drives the outputs low when the correspond- ing LVDS input is open, undriven and shorted, or undriven and parallel terminated. The fail-safe on the LVDS clock input drives all outputs low ...
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... LVDS inputs, and digital signals is recom- mended. The MAX9210/MAX9214/MAX9220/MAX9222 ESD toler- ance is rated for IEC 61000-4-2, Human Body Model and ISO 10605 standards. IEC 61000-4-2 and ISO 10605 specify ESD tolerance for electronic systems. The IEC ...
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... The MAX9210/MAX9214 have a rising-edge output strobe, which latches the parallel output data into the next chip on the rising edge of RxCLK OUT. The MAX9220/MAX9222 have a falling-edge output strobe, which latches the parallel output data into the next chip on the falling edge of RxCLK OUT. The deserializer out- put strobe polarity does not need to match the serializ- er input strobe polarity ...
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... LVDS CLOCK RECEIVER RxCLK IN+ 7x/9x PLL RxCLK IN- DCB/NC PWRDWN Chip Information MAX9210 TRANSISTOR COUNT: 10,248 MAX9214 TRANSISTOR COUNT: 10,248 MAX9220 TRANSISTOR COUNT: 10,248 MAX9222 TRANSISTOR COUNT: 10,248 PROCESS: CMOS ______________________________________________________________________________________ Programmable DC-Balance DATA TOP VIEW CHANNEL 0 RxOUT0–6 SERIAL-TO- PARALLEL CONVERTER DATA CHANNEL 1 RxOUT7– ...
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... Programmable DC-Balance 21-Bit Deserializers (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) N MARKING AAA TOP VIEW SIDE VIEW NOTES: 1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH. ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © ...