ICS9173-01CS08LFT IDT, Integrated Device Technology Inc, ICS9173-01CS08LFT Datasheet - Page 3

• Manufacturer Part Number: ICS9173-01CS08LFT
• Description: IC VIDEO GENLOCK PLL 8-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Multiplier/Dividerr

Specifications of ICS9173-01CS08LFT

• Applications: Video Camera
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1815-2; 9173-01CS08LFT

Using the IDT9173B in Genlock Applications
Most video sources, such as video cameras, are
asynchronous, free-running devices. To digitize video or
synchronize one video source to another free-running
reference video source, a video “genlock” (generator lock)
circuit is required. The IDT9173B integrates the analog
blocks which make the task much easier.
In the complete video genlock circuit, the primary function of
the IDT9173B is to provide the analog circuitry required to
generate the video dot clock within a PLL. This application
is illustrated in Figure 1. The input reference signal for this
circuit is the horizontal synchronization (H-SYNC) signal. If
a composite video reference source is being used, the
h-sync pulses must be separated from the composite signal.
A video sync separator circuit, such as the National
Semiconductor LM1881, can be used for this purpose.
The clock feedback divider shown in Figure 1 is a digital
divider used within the PLL to multiply the reference
frequency. Its divide ratio establishes how many video dot
clock cycles occur per h-sync pulse. For example, if 880
pixel clocks are desired per h-sync pulse, then the divider
ratio is set to 880. Hence, together the h-sync frequency and
external divider ratio establish the dot clock frequency:
f
Both input pins IN and FBIN respond only to negative-going
clock edges of the input signal. The H-SYNC signal must be
constant frequency in the 12 kHz to 1 MHz range and stable
(low clock jitter) for creation of a stable output clock.
The output hook-ups of the IDT9173B are dictated by the
IDT™ VIDEO GENLOCK PLL
OUT
IDT9173B
VIDEO GENLOCK PLL
= f
IN
x N where N is external divide ratio
Figure 1: Typical Application of IDT9173B in a Video Genlock System
3
desired dot clock frequency. The primary consideration is
the internal VCO which operates over a frequency range of
10 MHz to 75 MHz. Because of the selectable VCO output
divider and the additional divider on output CLK2, four
distinct output frequency ranges can be achieved. The
following Table lists these ranges and the corresponding
device configuration.
Note that both outputs, CLK1 and CLK2, are available
during operation even though only one is fed back via the
external clock divider.
Pin 5, OE, tristates both CLK1 and CLK2 upon logic low
input. This feature can be used to revert dot clock control to
the system clock when not in genlock mode (hence, when in
genlock mode the system dot clock must be tristated).
When unused, inputs FS0 and OE must be tied to either
GND (logic low) or VDD (logic high).
State
FS0
0
0
1
1
Output
Used
CLK1
CLK2
CLK1
CLK2
Frequency/Range
1.25 to 9.375 MHz
2.5 to 18.75 MHz
5 to 37.5 MHz
IDT9173B-01
10 to 75 MHz
IDT9173B
CLOCK SYNTHESIZER
0.625 to 4.6875 MHz
Frequency/Range
1.25 to 9.375 MHz
2.5 to 18.75 MHz
5 to 37.5 MHz
IDT9173B-15
REV A 092308