APU3146 Advanced Power Electronics Corp., APU3146 Datasheet - Page 5

     The  APU3046 IC combines a Dual synchronous Buck controller and a linear regulator controller, providing a cost-effective, high performance and flexible solution for multi-output applications

APU3146

Manufacturer Part Number
APU3146
Description
     The  APU3046 IC combines a Dual synchronous Buck controller and a linear regulator controller, providing a cost-effective, high performance and flexible solution for multi-output applications
Manufacturer
Advanced Power Electronics Corp.
Datasheet

Specifications of APU3146

Vin(min)
0.8
Vin(max)
16
Vout(min)
0.8
Vout(max)
5
Iout(max)
30
Frequency
200~500KHz
Power Good
?
Package
28-Pin TSSOP ,28-Pin SOIC
PIN DESCRIPTIONS
PIN#
1) These pins should not go negative (-0.5V), this may cause instability for the gate drive circuits. To prevent this,
a low forward voltage drop diode is required between these pins and ground as shown in Figure 1.
BLOCK DIAGRAM
SS2 / SD
SS1 / SD
26
27
28
Comp1
Comp2
V
V
Sync
V
SEN1
SEN2
POR
Gnd
Fb1
Vcc
Fb2
REF
V
Rt
P2
PIN SYMBOL
23
20
22
21
24
27
26
28
0.8V
8
4
6
7
5
2
V
Gnd
V
REF
25uA
P2
25uA
0.8V
64uA
Non-inverting input to the second error amplifier. In the current sharing mode, it is con-
nected to the programming resistor. In independent 2-channel mode it is connected to
V
Reference Voltage. The drive capability of this pin is about 2uA.
Analog ground for internal reference and control circuitry. Connect to PGnd plane with a
short trace.
REF
PIN DESCRIPTION
64uA
Max
pin when Fb2 is connected to the resistor divider to set the output voltage.
Error Amp1
Error Amp2
Figure 3 - Block diagram of APU3146.
Ramp2
Ramp1
Mode
VcH1
VcH2
PGood / OVP
Regulator
PWM Comp1
PWM Comp2
3.5V / 3.3V
4.2V / 4.0V
3.5V / 3.3V
Two Phase
Oscillator
Generator
Bias
Set1
Set2
UVLO
Shutdown
Thermal
Reset Dom
Reset Dom
S
R
R
S
OVP
HDrv OFF / LDrv ON
POR
Q
Q
3V
0.8V
Mode
0.3V
0.3V
SS2
SS1
SS1
SS2
3uA
0.8V
Control
Hiccup
V
P2
SS1
SS2
Control
3uA
Mode
20uA
20uA
POR
Mode
APU3146
18
17
15
16
19
10
11
25
13
12
14
9
1
3
PGnd1
OCSet1
Hiccup
PGnd2
OCSet2
V
V
LDrv1
VcH2
PGood
VcH1
HDrv1
HDrv2
LDrv2
OUT3
CL
5/28

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