APU3048 Advanced Power Electronics Corp., APU3048 Datasheet - Page 10

    The  APU3048 IC combines a Dual synchronous Buck controller and a linear regulator controller, providing a
cost-effective, high performance and flexible solution for multi-output applications

APU3048

Manufacturer Part Number
APU3048
Description
    The  APU3048 IC combines a Dual synchronous Buck controller and a linear regulator controller, providing a cost-effective, high performance and flexible solution for multi-output applications
Manufacturer
Advanced Power Electronics Corp.
Datasheet

Specifications of APU3048

Vin(min)
1.25
Vin(max)
25
Vout(min)
1.25
Vout(max)
5
Iout(max)
10
Frequency
200KHz
Scp
?
Otp
?
Package
16-pin TSSOP, SOP-16

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APU3048
Cross Over Frequency:
The stability requirement will be satisfied by placing the
poles and zeros of the compensation network according
to following design rules. The consideration has been
taken to satisfy condition 14 regarding transconduc-
tance error amplifier.
1) Select the crossover frequency:
2) Select R
3) Place first zero before LC’s resonant frequency pole.
4) Place third pole at the half of the switching frequency.
5) Place R
6) Place second pole at ESR zero.
7) Place second zero around the resonant frequency.
Fo < F
F
F
Where:
V
V
Lo = Output Inductor
Co = Total Output Capacitors
C
F
C
C
If not, change R
C
F
R
Check if R
If R
F
R
Z1
O1
P3
P2
Z2
IN
OSC
11
12
12
10
8
6
=
=
= F
8
= F
=
= Maximum Input Voltage
=
=
> 50pF
[
= R
is too small, increase R
2p 3 C10 3 F
2p 3 C10 3 F
75% F
= Oscillator Ramp Voltage
2p 3 F
f
ESR
2
2p 3 R
ESR
LC
S
2p 3 Lo 3 F
7
7
3C
7
, so that R
in (15) and calculate C
and Fo [ (1/10 ~ 1/6)3 f
8
LC
>
10
1
1
1
3
1
Z1
g
7
1
7
m
3 F
3 R
V
R
V
selection.
OSC
7
IN
7
P3
P2
Z2
7
O
3
>>
3 Co
- R
2p3Lo3Co
g
8
2
m
7
and start from step 2.
3
1
10
V
:
V
OSC
S
IN
---(15)
8) Use equation (1) to calculate R
These design rules will give a crossover frequency ap-
proximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load tran-
sient speed. The gain margin will be large enough to
provide high DC-regulation accuracy (typically -5dB to -
12dB). The phase margin should be greater than 458 for
overall stability.
LDO Section
Output Voltage Programming
Output voltage for LDO is programmed by reference volt-
age and external voltage divider. The Fb3 pin is the in-
verting input of the error amplifier, which is internally ref-
erenced to 1.25V. The divider is ratioed to provide 1.25V
at the Fb3 pin when the output is at its desired value.
The output voltage is defined by using the following equa-
tion:
LDO Power MOSFET Selection
The first step in selecting the power MOSFET for the
linear regulator is to select the maximum R
on the input to the dropout voltage and the maximum
load current.
Note that since the MOSFET R
perature, this number must be divided by ~1.5 in order
to find the R
has a maximum of 0.05V R
which meets our requirements.
R
For:
V
V
R
V
Results to: R
R
For:
V
V
I
Results to: R
OUT2
5
OUT2
REF
LOW
OUT2
DS(ON)
IN3
OUT2
=
= 3.3V
= 1.25V
= 2A
= 1K
V
= 2.5V
= V
= 2.5V
OUT
DS(ON)(MAX)
=
V
REF
V
REF
- V
IN3
3 1+
HIGH
DS(ON)(MAX)
I
REF
OUT2
- V
(
=1K
at room temperature. The AP20T03GH
OUT2
3 R
R
R
HIGH
LOW
6
= 0.4V
DS(ON)
)
DS(ON)
at room temperature,
5
:
increases with tem-
DS(ON)
based
10

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