IR3500VMPBF International Rectifier, IR3500VMPBF Datasheet - Page 13

• Manufacturer Part Number: IR3500VMPBF
• Description: The IR3500V Control IC combined with one or more xPhase3 Phase IC implement the control and MOSFET driver functions for a VR11.1 CPU VTT power supply.
• Manufacturer: International Rectifier

Specifications of IR3500VMPBF

• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available

VID Control
The VID pins require an external bias voltage and should not be floated. The VID input comparators monitor the VID
pins and control the Digital-to-Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier. The
output of the buffer amplifier is the VDAC pin. The VDAC voltage, input offsets of error amplifier and remote sense
differential amplifier are post-package trimmed to provide 0.7% system set-point accuracy. The actual VDAC
voltage does not directly determine the system accuracy, which has a wider tolerance.
The IR3500V can accept changes in the VID code while operating and vary the DAC voltage accordingly. The slew
rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and LGND pin. A
resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier. Digital VID
transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush
currents in the input and output capacitors and overshoot of the output voltage.
ROSC/OVP
VCCLDRV
VCCLFB
ENABLE
CLKOUT
PHSOUT
SS/DEL
VIDSEL
PHSIN
VDAC
VCCL
LGND
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VO
Page 13 of 34
OV@START
VCCL-1.2V
Float
Voltage
3.5k
800mV
INTEL
850mV
CLKOUT
PHSOUT
VCCL REGULATOR
AMPLIFIER
VID0
VBIAS
PHSIN
0.6V
1.19V
0.86
VCCL UVLO
VID4
VID2
0.6V
3.3V
+
-
OV@OPERATION
AMD
ENABLE
COMPARATOR
VID5
VID3
VID1
VID0
-
+
VIDSEL
VIDSEL
VIDSEL
VIDSEL
VID7
VID6
VIDSEL
COMPARATORS
VID INPUT
COMPARATORS
(1/8 SHOWN)
0.86
1.14V
0.94
1.2V
AMD 1.0V
INTEL 0.6V
VCCLDRV
IROSC
+
-
VCCL OUTPUT
COMPARATOR
+
-
80mV
120mV
4.0V
250nS
BLANKING
FAULT
ROSC BUFFER
AMPLIFIER
VID5
VID3
VID1
VID4
VID7
VID6
VID2
AMD 6-BIT
VR11 BOOT
VR11 NoBOOT
OPEN DAISY
CHAIN
AMD 5-BIT
INTERNAL
DIGITAL
TO ANALOG
CONVERTER VBOOT
+
-
VDAC
DELAY
COMPARATOR
VID0
VCCL UVLO
VIDSEL
+
-
DISCHARGE
COMPARATOR
0.2V
VIDSEL
VBOOT
VID
FAULT
LATCH
(1.1V)
DVID
-
+
CURRENT
SOURCE
GENERATOR
S
R
POWER OK
LATCH
IROSC
1.3uS
BLANKING
Q
Figure 8 – IR3500V Block Diagram
VBOOT
LATCH
SET
DOMINANT
SS RESET
Q
RESET
DOMINANT
S
R
S
R
DYNAMIC VID DETECT
COMPARATOR
Q
SAMPLE DELAY
+
-
ISOURCE
ISINK
VCCL
EAOUT
+
-
VDAC BUFFER
AMPLIFIER
1.08V
50mV
OV FAULT
VID FAULT
LATCH
FAULT LATCH1
FAULT LATCH2
SET
DOMINANT
R
S
VID SAMPLE
DELAY
COMPARATOR
-
+
OC DELAY
8-Pulse
Delay
+
-
Q
RESET
3.2V
1.6V
130mV
3mV
OC
OPEN VOLTAGE LOOP
IDCHG
OC LIMIT
AMPLIFIER
4.5uA
200mV
OC after VRRDY
VID FAULT LATCH
OPEN SENSE LINE
OPEN DAISY CHAIN
VDAC
OC LIMIT
COMPARATOR
OPEN SENSE
LINE DETECT
COMPARATORS
OC DELAY
COUNTER
-
+
VO
60mV
OC before VRRDY
+
-
OVER
VOLTAGE
COMPARATOR
VID FAULT
VCCL UVLO
-
+
DISABLE
+
-
315mV
275mV
DIS
OPEN SENSE LINE
IROSC
PHSOUT
+
-
DETECTION
PULSE
REMOTE SENSE
AMPLIFIER
VO
RESET
+
-
SS RESET
VCCL UVLO
UNDER
VOLTAGE
COMPARATOR
25k
SS CLEARED
FAULT LATCH1
UV CLEARED
FAULT LATCH2
IROSC
IOCSET
25k
+
-
SOFT
START
CLAMP
UV
VIDSEL
DETECTION
PULSE
SET
DOMINANT
SET
DOMINANT
+
-
S
R
S
R
IVOSEN+
25k
25k
Q
Q
1.4V
1.73V
POWER NOT OK
FAULT LATCH1
VCCL
FAULT LATCH2
POWER-UP OV
COMPARATOR
IVOSEN-
OV FAULT
OV@START
OV@OPERATION
ERROR
AMPLIFIER
IROSC
-
+
OPEN SENSE
LINE DETECT
COMPARATORS
ENABLE
July 28, 2008
1.5V
VRHOT COMPARATOR
1.6V
OV@OPERATION
IVOSEN-
-
+
-
+
VCCL UVLO
UV
VCCL
+
+
-
1
2
3
4
5
VDRP AMPLIFIER
-
+
IR3500V
ISETPT
VCCL*0.9
DISABLE
0.4V
OV FAULT
LATCH
+
-
400K
SET
DOMINANT
S
R
6
Q
VCCLDRV
OV@START
OV FAULT
VCCL
PGOOD
HOTSET
VRHOT
IIN
OCSET
VDRP
EAOUT
FB
VSETPT
VOSEN+
VOSEN-