FAN302UL Fairchild Semiconductor, FAN302UL Datasheet - Page 15
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FAN302UL
Manufacturer Part Number
FAN302UL
Description
This highly integrated PWM controller provides several features to enhance the performance of flyback converters
Manufacturer
Fairchild Semiconductor
Datasheet
1.FAN302UL.pdf
(19 pages)
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.2
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a 150ns leading-edge
blanking time is built in. Conventional RC filtering can
therefore be omitted. During this blanking period, the
current-limit comparator is disabled and it cannot switch
off the gate driver.
Noise Immunity
Noise from the current sense or the control signal can
cause
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoid long PCB
traces and component leads and, locate bypass filter
components near the PWM IC.
significant
Figure 41. V
pulse-width
S
OVP Protection
jitter.
While
slope
15
Test Mode
To facilitate production wafer sorting and to tighten
some of the specificiations, FAN302UL has two test
mode, depending on the voltage level at the CS pin and
the VS pin.
When the voltage the at the CS pin is greater than 3.5V,
FAN302UL enters Test Mode 1. Test Mode 1 disables
OCP, OTP, and frequency-hopping functions. This test
mode is used to measure the V
through the FB pin, I
and f
gate pin.
When the voltage at the VS pin is greater than 5.5V,
FAN302UL enters Test Mode 2 to disable frequency-
hopping function. This test mode is only used to
measure the V
for constant current putput) throught the FB pin.
When using the test modes, to measure V
V
pin must be disabled by triggering V
the
accuracy. In the f
the test modes disables the frequency-hopping function
to improve measurement accuracy.
CCR
in the ATE tester; the switching pulse at the gate
switching
osc
(maximum switching frequency) through the
CCR
noise
osc
(variation test voltage on the CS pin
TC
measurement by ATE tester, using
(bias current) through the VS pin,
and
improve
VR
(reference voltage)
DD-OVP
measurement
www.fairchildsemi.com
to decrease
VR
, I
TC
, and