FAN6300A Fairchild Semiconductor, FAN6300A Datasheet - Page 4
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FAN6300A
Manufacturer Part Number
FAN6300A
Description
The highly integrated FAN6300A/H of PWM controller provides several features to enhance the performance of flyback converters
Manufacturer
Fairchild Semiconductor
Datasheet
1.FAN6300A.pdf
(15 pages)
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© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
Pin Configuration
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
Name
GATE
GND
VDD
DET
CS
NC
HV
FB
- Generates a ZCD signal once the secondary-side switching current falls to zero.
- Produces an offset voltage to compensate the threshold voltage of the peak current limit to
- Detects the valley voltage of the switching waveform to achieve the valley voltage switching
Description
This pin is connected to an auxiliary winding of the transformer via resistors of the divider for
the following purposes:
A voltage comparator and a 2.5V reference voltage develop a output OVP protection. The ratio
of the divider decides what output voltage to stop gate, as an optical coupler and secondary
shunt regulator are used.
The feedback pin should to be connected to the output of the error amplifier for achieving the
voltage control loop. The FB should be connected to the output of the optical coupler if the
error-amplifier is equipped at the secondary-side of the power converter.
For the primary-side control application, FB is applied to connect a RC network to the ground
for feedback-loop compensation.
The input impedance of this pin is a 5kΩ equivalent resistance. A 1/3 attenuator connected
between the FB and the PWM circuit is used for the loop-gain attenuation. FAN6300A/H
performs an open-loop protection once the FB voltage is higher than a threshold voltage
(around 4.2V) more than 55ms.
Input to the comparator of the over-current protection. A resistor senses the switching current
and the resulting voltage is applied to this pin for the cycle-by-cycle current limit.
The power ground and signal ground. A 0.1µF decoupling capacitor placed between VDD and
GND is recommended.
Totem-pole output generates the PWM signal to drive the external power MOSFET. The
clamped gate output voltage is 18V.
Power supply. The threshold voltages for startup and turn-off are 16V and 10V, respectively.
The startup current is less than 20µA and the operating current is lower than 4.5mA.
No connect
High-voltage startup.
provide a constant power limit. The offset is generated in accordance with the input voltage
when PWM signal is enabled.
and minimize the switching losses.
Figure 4. Pin Configuration
4
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